Abstract: A very thin portable computer includes a computer housing for holding electronic components and a battery housing movably mounted external to the computer housing, the battery housing adapted for holding batteries for supplying power to the electronic components. The battery housing is rotatably mounted on the computer housing such that the battery housing rotates between a closed position wherein the battery housing covers the rear side of the computer and an open position wherein the battery housing exposes connectors on the computer housing and elevates the rear side of the computer housing to an angle convenient for typing.

Abstract: An apparatus and method of implementing an enhanced PCI interrupt controller which accommodates the industry standard wire-or functionality. With such an arrangement a method and apparatus to identify a source of a PCI interrupt without the need for polling is implemented with a register-based architecture and staged initiator decode. The invention implements both the default industry standard and a non-polled (interrupt accelerator) mode.

Abstract: A forwarding information management system for a bridge or router is disclosed, including a method and apparatus for merging free space segments in a forwarding table. The forwarding table is allocated into forwarding entry sets and free space queues. Each forwarding entry set must be within a single contiguous block of the forwarding table memory. A set of free queues is used to manage the free space segments in the forwarding table that are not allocated into forwarding entries. Each free queue maintains pointers to free space segments of a particular size. The forwarding table becomes fragmented as forwarding entries are added. A table packing process is triggered by a predetermined trigger to merge small areas of free space into large areas of free space, making consecutive forwarding entry sets contiguous in order to combine small areas of free space into larger ones.

Abstract: A program for monitoring computer system performance includes a collection of source code modules in the form of a high level language. Each of the source code modules is compiled into a corresponding object code module. The object code modules are translated into a single linked code module in the form of a machine independent register transfer language. The linked code module is partitioned into basic program components. The basic program components include procedures, basic blocks within procedures, and instructions within basic blocks. Fundamental instrumentation routines identify, locate, and modify specific program components to be monitored. The modified linked code module is converted to machine executable code to be executed in the computer system so that performance data can be collected while the program is executing in the computer.

Abstract: In a computer system, events indicative of the performance of the system are generated by system hardware and software. A user requests control of counters of different designs for counting the events. If the request for control of the counters is granted, a set of events is selected for monitoring according to predetermined attributes which characterize the events. A determination is made if the events of the set are valid, and they are determined to be valid, each event of the set are coupled to a corresponding one of the counters. The counters are then enabled to count the events of the set.

Abstract: An apparatus is provided for detecting the signaling frequency of communications signals transported on the trunk and lobe circuits of a token ring. The communications signals including Differentially Manchester Encoded data signals. The apparatus includes an internal trunk circuit and a plurality of ports including an input port for connecting to an input trunk segment, and an output port for connecting to an output trunk segment, and a plurality of lobe ports for connecting to the lobe circuits. Means are provided for sensing the frequency of the data signals at each of said plurality of ports. The sensing means including means for taking multiple successive timing samples, and grouping the samples into quality groups.

Abstract: In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.

Abstract: An apparatus for establishing timing signals of a communications network includes a plurality of ports and an internal trunk circuit for interconnecting trunk segments and lobes of the network. A speed detection circuit connected to each of said plurality of ports, are provided for sensing a plurality of timing signals, there being one timing signals sensed at each of the plurality of ports. The apparatus establishes a timing signal on the internal trunk equal to the timing signal senses at a majority of the ports to enable a majority of the nodes connected to a majority of the plurality of lobe ports to transport communications signals via the network.

Abstract: In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.

Abstract: When two asynchronous signals may occur at approximately the same time, only one of the signals being able to control consequent events, a circuit accounts for the conflict situation by selectively adding a delay until the conflict situation has settled. While the circuit does not determine which asynchronous event may control, the selective delay extends the time for the decision to be made. This circuit provides high reliability while minimizing delays and eliminates the need for indiscriminately adding a delay to each asynchronous event so as to resolve conflict situations. The circuit has particular applicability to volatile memory systems wherein conflict between processor requests and refresh requests to memory occur and allows processor requests to proceed with minimum delay in nearly all situations.