Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit. Each structure includes one or more MOS transistors, each of which exhibits a threshold voltage that varies with misalignment in one dimension. The test structures are configured in mirrored pairs, so that misalignment in one direction oppositely affects the threshold voltages of the paired structures. The threshold voltages of the paired structures can therefore be compared to determine the extent and direction of misalignment. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between active implants and the windows in which active regions are formed.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: Described are a system and method for converting a typical two-level logic signal to a pair of differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output terminals. A resistor network connected to these output terminals converts the complementary signals to a pair of differential signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract: Described are systems and methods that take advantage of the run-time reconfigurability of modern programmable logic devices to efficiently implement content-addressable memory (CAM) circuits. Rather than using configurable logic to compare CAM entries stored in flip-flops, a CAM in accordance with the invention uses configurable logic for both data storage and comparison. A CAM in accordance with one embodiment of the invention includes a number of programmable look-up tables on a programmable logic device collectively configured to produce a “match” signal in response to data provided on a series of data input terminals. Configuration data determines the particular pattern to which the CAM responds, so new CAM entries are introduced by configuring (or reconfiguring) one or more of the look-up tables.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: A programmable logic device (PLD), such as a field-programmable gate array (FPGA), includes an integrated delay-locked loop that produces a lock signal internal to the FPGA. The FPGA also includes a sequencer and related global signals adapted to configure the FPGA using external configuration data. The sequencer disables the FPGA during the configuration process. The sequencer then continues to disable the fully configured FPGA until receipt of the lock signal. The configuration process, including the establishment of a valid internal clock, is controlled entirely within the FPGA. In one embodiment, an FPGA can be fully or partially reconfigured without powering down the device. The delay-locked loop maintains a lock on the clock signal so that the sequencer need not wait for the lock signal after reconfiguration.

Abstract: An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

Abstract: A circuit measures a signal propagation delay through a series of memory elements on a programmable logic device. In one embodiment, a number of latches are configured in series. Each latch is initialized to store a logic zero. The first latch is then clock-enabled so that the output of the latch rises to a logic one. The logic one from the first latch clock-enables the second latch in the series so that the output of the second latch rises to a logic one, which in turn enables the next latch in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each latch to change in response to a clock-enable signal. Consequently, the delay through the series of latches provides a measure of the time required for one of the latches to respond to a clock-enable signal.

Abstract: A circuit separately measures one or both of the rising-edge and falling-edge signal propagation delays through a signal path of interest. The greater of these delays can then be used to establish a worst-case delay for the signal path. The worst-case delay can be used, in turn, to create accurate timing specifications for logic circuits that include similar or identical signal paths. To determine the delay through the signal path, the signal path is used with a second, typically identical, signal path to create alternating feedback paths of an oscillator. The oscillator is configured to output a test-clock signal having a period proportional to either the rising- or falling-edge delays through the two signal paths. The test-signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the signal path of interest.

Abstract: A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: Described is a user-controlled, variable-delay interconnect structure for a programmable logic device (PLD), and a method for using this structure. In accordance with the invention, the signal propagation delays for selected signal paths can be precisely adjusted either while the PLD is being programmed or while the PLD is operating as a logic device. The delays are adjusted by selectively connecting otherwise unused interconnect lines to the signal path to increase the capacitive load on the interconnect lines that define the signal path. The ability to control the load on selected signal paths advantageously enables a user to precisely match the signal propagation delays of two or more signal paths. In one embodiment, the loads of selected signal paths can be modified while the FPGA is operational.