Abstract: To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.

Abstract: A large scale sequential integrated circuit is made amenable to scan design testing by the inclusion of special multiplexing and storage circuits which respond to a pair of test control pulses to reconfigure the circuit to include one or more shift registers and to step the scan test data through the shift registers. In particular, the pair of test control pulses are applied to the two terminals to which, in normal operation, are applied the clock pulses which are used to control the storage elements and which, in such operation, are never both simultaneously high. To initiate the scan test operation, these test control pulses are made simultaneously high and the circuitry responds to such conditions.

Abstract: A photodetector useful at long wavelengths where silicon normally is transparent. It includes a photodiode stage which comprises a silicide layer forming a Schottky-barrier junction with a silicon substrate and which is integrated with an amplification stage which uses a silicon transistor adapted to amplify the photovoltaic voltage derived by the photodiode stage. In the preferred embodiment, the silicide layer forms the grid of a permeable base transistor.

Abstract: To improve the speed of transfer of information to the databus in data processing apparatus, the bus is periodically precharged and the coupling to the databus is by way of a special clocked CMOS buffer circuit.

Abstract: An avalanche photodetector useful at wavelengths as long as 1.7 microns with low noise is achieved. The crystal used includes successive layers of p-type indium phosphide, n-type indium phosphide, and n-type indium gallium arsenide. An appropriate total of fixed charges in the n-type indium phosphide and a graded bandgap heterointerface region are important for the improved results.

Abstract: The present invention is a one-bit full adder circuit having a fast carry. The circuit may be implemented using integrated injection logic in which case the circuit comprises six NAND gates and two wired AND gates. Advantageously, there is only a single gate delay in the carry path.

Abstract: A light emitting diode designed to emit primarily at 1.3 microns comprises a crystal having a plurality of lattice matched layers including an n-type indium phosphide front surface layer, an n-type indium phosphide buffer layer, a p-type indium gallium arsenide phosphide active layer, a p-type indium phosphide confining layer and an indium gallium arsenide back surface layer, and an annular front contact and a limited area back contact to the crystal.

Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

Abstract: Disclosed is an eight-mask twin-tub CMOS process which forms contiguous p- and n-tubs in a relatively lightly doped bulk region in a self-aligned manner using a single masking step. The process also forms the sources and drains of the p- and n-channel transistors with a single masking step by first nonselectively implanting p-type impurities into all source and drain regions and then selectively implanting n-type impurities into only the source and drain regions of the n-channel transistors in amounts sufficient to overcompensate the p-type impurities therein.

Abstract: In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the transistors in the string, the switching-delay is not significantly reduced by uniformly increasing the conduction channel widths of the transistors in the string. However, according to the present invention, a substantial reduction in the switching delay of such a circuit may be obtained by scaling the conduction channel widths of the transistors in the string so as to provide a positive gradient in conduction channel widths along the string in the direction from the output terminal to the power supply terminal. It is particularly advantageous to use exponential scaling of the conduction channel widths.

Abstract: A power-down network is included in a tristate TTL circuit to reduce power dissipation in the high impedance third state while permitting high switching speeds during bistate operation of the circuit. The power-down circuit includes a power-down transistor connected in series between the collector resistor and collector of the phase splitter transistor. The base of the phase splitter transistor is connected through a diode to the disabling gate. A first resistor having a significantly higher value than the collector resistor is connected between the base of the power-down transistor and the V.sub.CC terminal. When the circuit is in the high impedance state, the power-down transistor is turned off to interrupt current flow through the collector resistor, and a relatively high impedance current path through the first resistor to the disabling gate is substitute for an otherwise relatively low impedance current path through the collector resistor.

Abstract: In planar silicon semiconductor devices of the PN junction type, field plates overlie the silicon dioxide-silicon nitride film on the device surface to inhibit inversion formation of conductive channels on the device surface. The field plates are connected to a more heavily doped zone on one side of a PN junction and extend some distance over the lightly doped zone on the other side of the PN junction.At high reverse biases, the presence of trapping centers produces a charge level at the device surface, resulting in current channeling which produces excessive reverse leakage current. This effect is avoided or reduced by omitting the silicon nitride layer in a portion overlying the more lightly doped zone and spaced away from the PN junction boundary. This omission eliminates a portion of the oxide-nitride interface which appears to be the locus of such trapping centers.

Abstract: An optically toggled bidirectional normally-on switch is provided with protection against bilateral voltage and bidirectional current surges by the inclusion of a pair of oppositely poled thyristors. One version uses a large junction-type field-effect transistor in its main path and a pair of smaller junction-type transistors in the subsidiary path. A photodiode array controls the gate voltage on each of the transistors and turns them off when illuminated. A control node in the subsidiary path is connected to the gates of the SCRs so that excess current in this path turns on the appropriately-poled thyristor to provide an additional shunt path for the current.

Abstract: A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals.

Abstract: A static bipolar random access memory employs a novel layout for high packing density. Each cell uses a cross-coupled pair of NPN vertical transistors as drivers merged with a pair of PNP lateral transistors as loads, Schottky diode coupling to the input/output lines and Schottky diode clamping of the internal nodes. The PNP transistors are also partially merged between cells to conserve space. OXIL technology is used to achieve high gain vertical transistors and to provide dielectric isolation.

Abstract: A capacitor-resistor-capacitor (CRC) element for active filter realization, which is fully integrable and compatible with MOS technology, is described. The incorporation of the CRC element in a semiconductor integrated circuit active filter also is described. The structure of the CRC filter element is closely analogous to a depletion mode MOS field effect device, except that the channel zone 26 is doped to a level which substantially precludes conductivity modulation at the usual operating voltages. However, the doping level is such as to enable the use of the channel zone as a semiconductor resistance element. Thus, the N-channel CRC element realized in the NMOS technology comprises a first capacitance composed of the gate 27, gate dielectric 38, and resistive channel 26, paralleled by the resistive channel 26 itself constituting a resistor, and then the underlying PN junction capacitance between the N-type resistive channel 26 and the underlying P-type semiconductor body portion 21.

Abstract: The present invention is a method and apparatus for aligning a semiconductor wafer to be patterned by a step-and-repeat photolithographic system. The inventive alignment technique, which is able to compensate for local wafer tilt and/or nonuniform photoresist thickness, is applicable to semiconductor wafers which have, on a surface portion, one or more Fresnel zone plate alignment marks.

Abstract: A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified.

Abstract: A normally-OFF switch includes a transistor branch path and a parallel pair of oppositely poled thyristor branch paths to protect against voltage surges. To minimize latching-on of the thyristors as a result of voltage surges, the thyristor branch paths including light emitting diodes which light up when excess current flows in the thyristor branch paths and actuate a photodiode array which biases the transistor path to conduction to divert excess current from the thyristor path.

Abstract: Single wall domains are moved synchronously in a sheet of magnetic material along channels defined by magnetically soft overlays as an in-plane magnetic field reorients. A detector is described which includes as an integral part thereof a portion of the overlay defining the propagation channels.