Abstract: An integrated development environment on a client provides for developing transaction programs, web pages, and applets for execution on a high performance transactional based World Wide Web server. The transaction programs are developed on the client, then automatically transferred to the server, where they are automatically compiled, linked, loaded into a TP library, registered with a TP monitor for execution, and tested. Similarly, the web pages and applets are developed on the client, then automatically transferred to the server, loaded into a database, and tested.

Abstract: In a data processing system with multiple processors, failing processors are replaced with spare processors. This allows the system to continue to operate without degradation. An intercept process is notified of a processor failure so that it can collect processor registers and states. If the registers and states are collected correctly, an indication is set that relief is possible. The intercept process notifies a service processor of the failure and then halts the failed processor. The service processor then notifies the operating system of the failure and that relief is possible. If fast relief is acceptable, a spare processor is initialized and resumes execution with the state and registers of the failed processor. A service processor modeling file controls the number of active and spare processors in a system. Spare processors sharing the same L2 cache with the failed processor are preferred as replacements.

Abstract: In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

Abstract: A mass memory storage unit includes a cabinet and one or more drawers incorporated into the cabinet. Each drawer is movable between closed and open positions to permit access to the interior for service. Inside each drawer, there is a connector plane disposed generally to one side of the drawer interior and parallel to the direction of travel between the closed and open positions. The connector plane incorporates connectors for receiving storage devices (for example, hard disk drives), each incorporating a connector which detachably mates with one of the connectors on the connector plane. Support and interface devices are coupled to the connector plane by suitable complementary connectors. It is useful to provide a cable, which itself may be detachable from the connector plane, to establish a redundant connection such that the devices in a drawer remain in-circuit when that drawer is opened for access to the enclosed components.

Abstract: In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, selecting a working space base address data structure entry utilizing the corresponding working space number, determining a working space base address from that selected working space base address data structure entry, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address. A corresponding working space limit entry can be utilized to bounds check the addresses generated.

Abstract: When emulating a Target architecture on a Host system having a different architecture, virtual to real address translation is typically expensive in terms of computer cycles. The cost can be significantly reduced by utilizing direct page table pointers to short-circuit the address translation. In a system additionally supporting segments framing portions of virtual memory, the direct page table pointers are associated with segment registers and point to the page table entry corresponding to the first location in a segment. Direct page table pointers are invalidated when underlying virtual memory management tables are modified.

Abstract: A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits.

Abstract: In the emulation of a target system utilizing a multiprocessor (12) host system (10) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memory. The old contents of a word (48) in memory are loaded (80) into a first register (52). A loop is then entered. The contents of the first register (52) are copied (82) into a second (54). The contents of the second register (54) are then appropriately modified (84), depending on the instruction being emulated. After a lock (90), the two registers are compare-exchanged (86) with the memory word (48), resulting in the modified second register (54) being written to the memory word (48) if the contents of the first register (52) match. Otherwise, the compare-exchange instruction (86) loads the current copy of the word (48) into the first register (52), and the loop repeats.

Abstract: When emulating a Target architecture on a Host system having a different architecture, virtual-to-real address translation is typically expensive in terms of computer cycles. The cost for translating addresses for instruction fetches can be significantly reduced by maintaining both a virtual and a real memory address instruction counter. Both are incremented on each instruction fetch. Virtual to real address translation is eliminated as long as execution continues on the same real memory page of instructions. Alternatively, only a real memory address instruction counter is incremented, while maintaining a delta instruction counter value to efficiently translate back and forth to and from the corresponding virtual memory address.

Abstract: A data processing system with a RAID cache disk subsystem utilizes three RAID cache disk controllers to provide increased performance along with increased reliability, especially in the event of a failure of one of the disk controllers. Disk writes are mirrored in two disk controllers in order to guarantee integrity in the event of a disk controller or interface failure. Typically this write caching must be terminated when one of the controllers fails in order to maintain integrity. In the present invention, write caching continues utilizing the two remaining disk controllers.

Abstract: In order to obtain mixed and space efficient use of mass memory units having different form factors into a single package, a specially configured connector plane module is provided. The connector plane module includes three identical, aligned, connector plane connectors arranged in a new configuration. Two spaced apart connector plane connectors are disposed in the same orientation with one another; but the third connector plane connector is spaced apart from and disposed in 180° orientation with respect to the second connector. With this configurtion, two mass memory storage units having a first form factor or three mass memory storage units of a second, smaller, form factor may be coupled to the connector plane to occupy substantially the same space, one mass memory unit in each case being oriented at 180° with respect to the one or two other mass memory units.

Abstract: A data communications system for supporting World Wide Web (WWW) database queries to enterprise level databases utilizes two server based programs. A first program retrieves and transmits a specified version of a specified form to an intermediate forms program. The second program has two modes of operation. In either mode, database queries to the enterprise level database are performed and results transmitted. However, in a first, standard, mode of operation, a specific version of a specific form is read from a forms database and transmitted to the requester along with the query response. In the second mode of operation, only the database query results are transmitted, along with a modified header that specifies the appropriate form. The corresponding forms are retrieved from a local forms database and merged with the query response before being displayed by a Web browser. Missing forms are requested from the Web forms program and cached for subsequent requests.

Abstract: Interactions among multiple processors (92) are exhaustively tested. A master processor (92) retrieves test information for a set of tests from a test table (148). It then enters a series of embedded loops, with one loop for each of the tested processors (92). A cycle delay count for each of the tested processors (92) is incremented (152, 162, 172) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (176). In each such test (176), the master processor (92) sets up (182) each of the other processors (92) being tested. This setup (182) specifies the delay count and the code for that processor (92) to execute. When each processor (92) is setup (182), it waits (192) for a synchronize interrupt (278). When all processors (92) have been setup (182), the master processor (92) issues (191) the synchronize interrupt signal (276). Each processor (92) then starts traces (193) and delays (194) the specified number of cycles.

Abstract: Instrumentation statistics are tallied at the procedure level in instrumentation stack frames corresponding to subroutine stack frames. Elapsed CPU time for each entry into a procedure is computed and accumulated into a statistics table corresponding to that procedure. Also accumulated into that statistics table are the accumulated elapsed execution times of the subroutines called by this procedure. These values are initially accumulated into the instrumentation stack frame for each subroutine's parent upon subroutine exit, and then accumulated into the statistics table upon subroutine exit of the parent. Elapsed CPU time is computed by subtracting CPU time of last dispatch from the current hardware clock, then adding this to an accumulated CPU time at the time of dispatch.

Abstract: A processor (92) in a data processing system (80) provides a DELAY instruction. Executing the DELAY instruction causes the processor (92) to a specified integral number of clock (98) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.

Abstract: A data processing system contains a processor supporting instructions and operands utilizing a Narrow word size. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. The translation between Narrow and Wide word sizes can be either at a byte/Unicode level, or at a word level.

Abstract: In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.

Abstract: A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe, constituting serially-coupled registers, is used to step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline.

Abstract: A pipelined processor for simultaneously performs one of a plurality of successive operations on each of a plurality of successive instructions within the pipeline, the successive operations including at least an instruction fetch stage, an operand address stage, an operand fetch stage, an execution stage and a result handling stage. The processor also maintains a plurality of indicators which are selectively updated during the result handling stage for a given instruction to reflect the results obtained during the execution stage thereof. When the second instruction of first and second successively fetched instructions is a conditional transfer, a determination is made as to which indicators may be affected by the execution of the first instruction, and a determination is also made as to which indicator the conditional transfer is to test to decide whether there is a GO or a NOGO condition.

Abstract: A mapping between terminal presentation and a Graphical User Interface to an end user using a web browser is provided. The mapping representation is created to support a selected screen image sent from the application to the web browser. A generic interpretative applet and the screen mapping representation is forwarded to a web server and in turn is downloaded to a web browser using a well known protocol. The applet generates and processes messages in an acceptable presentation, e.g. IBM 3270 format, and exchanges those messages directly with a receiving application across a computer network, thereby reducing or eliminating message translation and traffic through intermediate applications and systems.