Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
Type:
Grant
Filed:
August 8, 2002
Date of Patent:
September 7, 2004
Assignee:
Xilinx, Inc.
Inventors:
Srinivasan Dasasathyan, Guenter Stenz, Sudip K. Nag