Abstract: A pipelined microprocessor is provided including a latch circuit wherein a first transmission gate is electrically coupled in series with a second transmission gate between an output line of a first pipeline stage and an input stage of a subsequent pipeline stage. The latch circuit is controlled by a single clock signal wherein a delay element is employed to simultaneously enable both transmission gates upon an edge of the clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input line is electrically coupled to the output line. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input line is decoupled from the output line.

Abstract: A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its normal mode. In one embodiment, an interrupt control unit is coupled to the ICE interrupt line of the microprocessor core, and controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. If the debug interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, thereby, causing the microprocessor core to execute ICE code.