Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Methods and circuitry for implementing monolithic high gain wideband amplifiers. The invention implements an amplifier with a limiter that also performs a signal dividing function. In a specific embodiment, the limiter is designed to make available two in-phase outputs that are then used to drive two gate input lines of a combiner distributed amplifier.

Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Abstract: A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The prepackaged PLDs and the ability to use the substrate as a burn-in vehicle for the FPIC die results in reliable and reworkable assembly process with minimized yield loss.

Abstract: Method and circuitry for implementing VCOs with improved frequency band switching use differentially-coupled varactors to implement the different frequency bands. According to a specific embodiment, one side of a varactor couples to the tank circuit and the other side is coupled either to ground or to the positive power supply VDD without introducing any series parasitic resistance.

Abstract: Method and circuitry for implementing an integrated differential termination resistance that is self-tracking. The invention employs a mechanism that automatically tracks variations on a number of circuit and signal parameters including input common-mode voltage, as well as varying device characteristics due to fluctuations in processing, power supply voltage and temperature. It then adjusts the resistance across the two differential input signals in a self-calibrating manner to obtain a substantially constant termination resistance for a given application.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.

Abstract: Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator. After the circuit determines that the internal oscillator signal has settled, contents of non-volatile register are read to select the clock source for the circuit. Upon successful selection and clean up of system clock, the reset is removed.

Abstract: A memory device having an array of memory cells distributed into rows and columns with a plurality of interconnects extending across the array and coupled to carry write data during a first period of time and control data during a second period of time. In some embodiments where data I/O pads, input buffers, I/O sense amplifiers, write drivers, and color registers are collectively located on an opposite side of the array away from column decoders, column pre-decoders and column redundancy circuits, time-sharing of write data and control data on a single bus significantly improves layout efficiency.

Abstract: A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.

Abstract: A semiconductor bilateral switch that minimizes the on-state resistance by making a common-source connection between the switch transistors internal to the package. Wire bonds internally connecting the source electrodes of the transistors also provide the function of one or both of a current sense resistor and fuse element.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A circuit for programmably grounding (or coupling to the positive rail) unused outputs to improve noise immunity of the circuit. The circuit of the present invention achieves, for example, programmable grounding of an output via already existing test signal paths, without introducing delays in speed critical output signal paths.

Abstract: A system and method implemented in hardware are provided to optimize rendering of a computer graphics image, which may be displayed in an image frame comprising a number of tiles. The system and method determine each tile in the image frame touched by a geometry (e.g., a triangle). Graphics data for the geometry is selectively stored into a separate, corresponding portion of memory for each tile touched by the geometry. The graphics data stored in each portion of memory can be readily accessed and used to render a portion of the image in the respective tile of the image frame.

Abstract: A method and apparatus for implementing an improved pulse width modulation circuit is disclosed. In particular, a circuit and method is provided to generate a pulse width modulated signal, wherein the circuit and method significantly reduce susceptibility to transient noise effects. The pulse width modulator according to the present invention operates at high frequencies and over a full duty cycle range of 0% to 100%. Furthermore, automatic self-correction logic is also disclosed for pulse width modulated circuits wherein the self-correction logic prevents fault conditions.