Abstract: A Conductive Epoxy Coating (“CEC”) process is provided for assembling semiconductor devices. The CEC process includes application of a conductive epoxy coating prior to wafer dicing and instead of dispensing epoxy/solder when performing die bonding. The CEC process generally begins with a silicon wafer. Processing of the silicon wafer includes coupling a conductive epoxy layer to a first side of the semiconductor wafer to form a coated wafer. The process cures the coated wafer and forms die from the coated wafer. The process further couples an exposed side of the conductive epoxy layer of the die to a lead frame to form a semiconductor device, and cures the semiconductor device.

Abstract: Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.