Abstract: A collapsible container liner for use within a bulk container having a substantially rigid top, bottom and side walls and a filler opening in the top wall. The liner is a collapsible bag of a flexible material with top, bottom and sides which correspond to the container walls within the interior of the container. A first opening in the liner top corresponds to the filler opening in the container top wall. A seal is formed between the container top wall and the liner top around the periphery of the filler opening and the first opening. A second opening in the liner top is spaced from the first opening and has an evacuation outlet attached to the liner top around the periphery of the second opening. Air is evacuated through the outlet from the space between the liner and the interior of the container, a vacuum forms which collapses the liner against the container interior surfaces.
Abstract: The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any type of advanced testing to be performed on the memory array without regard to the restrictions imposed by the various status flags that may be present. The testing mode can be entered by a completely user-defined mechanism. During this testing mode, the user has complete control over the contents of the memory array and can also have complete control over the positioning of the write word line with respect to the read word line without, for example, any write-read word line pointer equality signals being generated. In one example of the present invention used in a FIFO, testing times required for data retention testing are reduced from approximately six seconds to approximately 500.mu.
Type:
Grant
Filed:
December 5, 1995
Date of Patent:
June 24, 1997
Assignee:
Cypress Semicondcutor Corporation
Inventors:
Roland T. Knaack, Andrew L. Hawkins, Richard A. Rodell, Jr.