Abstract: A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address translation before source data operands are available. A store data queue snoops the finish buses of execution units for the source operand. A data entry in the data queue that is allocated at dispatch of the store instruction snoops for the source operand required by its corresponding instruction. The data operand is then communicated to a memory device in instruction order thereby simplifying the detection of conflicting stores.

Abstract: An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.

Abstract: A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.

Abstract: Method and apparatus for creating benchmark programs for the analysis of java virtual machine implementations are implemented. Java applications and applets are compiled into an intermediate code referred to as byte code. The Java byte code forms the machine code for the Java Virtual Machine. The Java Virtual Machine running on top of a hardware platform translates the byte code into native machine code for execution on the hardware platform on which the Java Virtual Machine is running. The performance of a Java Virtual Machine is improved by the use of a so-called "just in time" (JIT) compiler that translates commonly occurring sequences of bytes codes in the native instruction sequences which are then stored for later execution. Critical to the performance of the JIT is the ability of the JIT to optimally compile for the most commonly occurring sequences of byte codes. The method and apparatus for creating benchmark programs provides a means for performance measurements with respect to such sequences.

Abstract: A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.

Abstract: The present invention allows market participants to exchange bundles of assets, including assets in different asset classes. A market participant may value the bundle as an entity, alleviating the need to attempt to attain a value objective in the aggregate by valuing and trading assets individually. A bundle of assets to be traded is entered, wherein proportions of each asset to be traded in units of a specified bundle size are provided by the market participant. Assets to be acquired by one market participant are matched against the same asset which other market participants are seeking to dispose. An exchange of bundled assets among market participants, in units of the bundles themselves is effected when the exchange satisfies a predetermined set of criteria.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports out-of-order floating point unit instruction execution. The FPSCR mechanism provides appropriate reporting of exceptions to a re-order buffer implemented within a data processing system to allow precise interrupts during out-of-order instruction execution. Additionally, the FPSCR mechanism allows for the retention of the appropriate status and control history information in an FPSCR rename buffer to allow the floating points status and control register to be maintained as though instructions were being executed in order. Additionally, the FPSCR mechanism generates the FPSCR's sticky exception status in concordance with reporting appropriate status to the previously mentioned re-order buffer and saving history into the FPSCR rename buffer.

Abstract: A method for accurately and precisely computing the output signal transition times in a clock distribution, or buffering, network of a data processing system is provided herein. This methodology may be implemented in transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. Furthermore, the static timing analysis techniques traditionally implemented are modified to more accurately compute signal delays and transition times at the outputs of a clock distribution network circuit.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled.

Abstract: A data processing system renders a real-world object on a display device to represent a storage space of the data processing system. The real-world object is displayed with various labels and indicators to provide information about the internal contents of the storage space represented by the object as well as the storage space itself. Such visual indicators allow an external user to access information about the contents of a storage space without actually opening the storage space or delving into the depths of the user interface to determine additional information. In addition to providing information about the storage space represented by the real-world metaphor, the data processing system also allows the external user to selectively name the storage space represented by the object in a useful manner.

Abstract: A memory and a method for communicating therewith are implemented, the memory having a plurality of memory cell groups. Each memory cell group contains a plurality of memory cells. Memory cell groups within each subset of a plurality of subsets of memory cell groups include the same predetermined number of memory cells. During a read operation, a local bitline associated with the memory cell group from which data is being read is coupled to a global bitline. Other local bitlines, associated with the memory cell groups not being accessed during the read are decoupled from the global bitlines. Following a read, the local and global bitlines are restored by a precharge operation.

Abstract: A voice command interface is implemented in a data processing system whereby a user may select any application which is currently running on the data processing system without having to manually modify a list of programs which may be accessed by a voice command and without having to request the program by its full name. To allow a user to access a program which is currently running on the data processing system, control within the data processing system ensures that a name of the program or application which is opened by an external user is added to a window list automatically. Similarly, a program which is no longer enabled by a user and running on the data processing system will be automatically removed from the window list. Additionally, the data processing system and methodology implemented therein allow an external user to speak merely a portion of a title of an application to access the application using a voice command.

Abstract: A garlic sauce includes garlic, slivered nuts, vinegar, water, oil, and salt. These ingredients are combined without the addition of exogenous starch. A method of preparing the garlic sauce includes preconditioning nuts with garlic by dry blending to form a substantially homogeneous dough-like mixture, mixing vinegar, water, and salt into the dough-like mixture to form a substantially homogeneous batter, and adding oil to the dough to form a uniformly chunky, crunchy, and spreadable sauce with a rich golden hue.

Abstract: A field emitter including an exposed wide band gap emission area in contact with and protruding from a planar surface of a conductive metal, and a method of making is disclosed. Suitable wide band gap materials (2.5-7.0 electron-volts) include diamond, aluminum-nitride and gallium-nitride; suitable conductive metals include titanium, tungsten, gold and graphite. The method includes disposing the wide band gap material on a substrate, disposing the conductive metal on the wide band gap material, and etching the conductive metal to expose wide band gap emission areas. The emission areas are well suited for large area flat panel displays.