Abstract: Memory devices, refresh logic and approaches to selectively refresh each row of memory cells within a memory device depending on whether or not each is marked as having data to be preserved.
Abstract: An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.
Type:
Grant
Filed:
March 30, 2001
Date of Patent:
June 29, 2004
Assignee:
Intel Corporation
Inventors:
Tak M. Mak, Michael R. Spica, Michael J. Tripp