Abstract: This invention discloses a method for switching SO (Service Option) to circuit data, including the following steps: step 1, a mobile station notifies a source BS (Base Station) and/or a target BS to switch SO to circuit data during a session; step 2, the source BS and/or the target BS negotiates with a mobile switching subsystem about switching SO to circuit data, and determines the bearer format parameters of the session through the negotiation; step 3, the source BS and/or the target BS makes a secondary service negotiation with the mobile station after the negotiation with the mobile switching subsystem succeeds; and step 4, after the negotiation with the mobile station succeeds, the source BS and/or the target BS conducts user interface service layer encapsulation on the circuit data according to a certain load format, and then transmits the encapsulated Real Time Transfer Protocol packets to the other BS.

Abstract: Wireless mesh networks (or “meshes”) are enabled for arbitrary interconnection to each other and may provide varying levels of coverage and redundancy as desired. Interoperability between meshes having differing configurations, internal operations, or both, may be freely intermixed and inter-operated in unrestricted combination. Enhanced explicit inter-bridge control protocols operate using pre-existing control packets. Pre-existing broadcast packet floods are used to learn the best paths across interconnected meshes (termed a “multi-mesh”). Enhanced routing protocols operating within each mesh may optionally examine information limited to the respective mesh when forwarding traffic, thus enabling robust multi-mesh scaling with respect to memory and processing time required by the routing protocols. Communication scalability is improved by enabling frequency diversity across the multi-mesh by configuring meshes within interference range of each other for operation at a plurality of frequencies.

Abstract: Storage gateway provisioning, configuration, and management functions provide mechanisms to specify and manage parameters and operations associated with storage gateways. The parameters may include any combination of VLAN topology, zoning behavior, LUN masking, bandwidth, and priority. The parameters may also include path information describing initiator to target associations, enabling load-balancing aggregations and multipathing redundancy. Parameters may be specified at relatively low-levels, describing specific HW elements, or may be specified at relatively high-levels, describing desired bandwidth and redundancy requirements, with SW determining low-level HW assignments. Configuration and management functions enable dynamic modification of storage gateway parameters (such as bandwidth between selected initiator and target pairs). Management functions also enable dynamic switchover from a primary path to a secondary path with respect to a storage device.

Abstract: Real time provisioning and management of fabric-backplane enterprise servers includes monitoring system status and configuration, displaying monitoring results, accepting user commands, and providing hardware and software management and configuration commands to the system. In one embodiment, an event is generated when a pluggable module is inserted into the system. In response to the event, the availability of the pluggable module is displayed to a system operator, and the operator enters a command to provision a server that includes the pluggable module. The server provisioning command is processed, resulting in a hardware configuration command being issued to the system, and an event indicating a status associated with processing the command is returned. The recognition of the inserted module, the display to the operator, and the processing of the server provisioning command occur in real time.

Abstract: A system, method, and computer program product are provided for increasing a lifetime of a plurality of blocks of memory. In operation, at least one factor that affects a lifetime of a plurality of blocks of memory is identified. Additionally, the plurality of blocks to write is selected, based on the at least one factor.

Abstract: A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: A system, method, and computer program product are provided for providing data redundancy in a plurality of storage devices. In operation, a number of writes to a plurality of storage devices is reduced. Additionally, after the reducing, data redundancy is provided utilizing a data redundancy scheme.

Abstract: Individual wireless devices communicate amongst each other exchanging identity information, authentication-state or both, thereby forming a collaborative-collection of wireless devices. This collaborative-collection of wireless devices offers improvements over individual wireless devices in three areas. First, device functions are affected by the group of devices that are active-members of the collaborative-collection, enabling improved functionality. Second, the times-of-membership and times-of-non-membership of the devices in the collaborative-collection are monitored and this information is used to affect the function of individual devices in the collaborative-collection, including improved security and authorization policies. Third, the authentication-state of the active-member devices in the collaborative-collection affects the function of the active-member devices in the collaborative-collection, also adding to improved security.

Abstract: System, apparatus, and methods are disclosed wherewith a group of independent wireless routing devices known as Service Points work cooperatively to form an ad hoc mesh communication network. The resulting Service Point Network is used to provide reliable address-directed communication services between devices attached by conventional means (wired or wireless) to respective Service Ports on any of the Service Points. Attached Utilizing Devices are not considered a part of the Service Point Network and need not contain any custom software or hardware related to the operations of the Service Point Network. Consequently, the networking technology used to form the Service Point Network is independent of the technology used for connecting devices to Service Points. Services for Utilizing Devices include both point-to-point as well as point-to-multi-point communication.

Abstract: Portable computing hosts, such as PDAs, are customized for use in diverse applications, such as media and game players, through use of a first-level removable expansion module having player-specific circuitry and a slot for a second-level removable module, such as a removable memory. For example, in combination with a connected or attached user interface device (e.g., earphones), these modules provide a host with external-interface circuitry and/or application-specific functions as well as second-level removable memory functions. The removable memory may be used to store and playback digitally encoded media such as music, audio, or video. The removable memory may also be used directly or predominantly by the player's application specific circuitry within the first-level removable expansion module.

Abstract: Computer hosts, such as PDAs, are customized for use in bar code scanner applications through use of a first-level removable expansion module having bar code related circuitry and a slot and internal connector for a second-level removable memory. In combination with a connected or attached I/O device for scanning bar codes, these modules provide embedded bar code scanning I/O adapter and/or application-specific functions as well as second-level removable memory functions. The removable memory may be used to store a backup copy of the scanned data for restoration in the event the original scan data is lost or corrupted. Restoration may occur using any interface compatible with the removable memory. The removable memory may also be used by the bar code scanner application specific circuitry within the first-level removable expansion module.

Abstract: The utility of portable computer hosts, such as PDAs (or handhelds), is enhanced by methods and apparatus for removable expansion cards having application specific circuitry, a second-level-removable memory, and optional I/O, in a number of illustrative embodiments. In addition to providing greater expansion utility in a compact and low profile industrial design, the present invention permits memory configuration versatility for application specific expansion cards, permitting easy user field selection and upgrades of the memory used in conjunction with the expansion card. Finally, from a system perspective, the present invention enables increased parallelism and functionality previously not available to portable computer devices.

Abstract: Methods and apparatus for closed-case removable expansion cards having a removable memory enhance the utility of portable computer hosts, such as PDAs. In both a first and second embodiments the closed-case removable expansion cards preferably use a Type II CompactFlash form factor. In the first embodiment the removable memory is in combination with an external-I/O connector or attached external-I/O device, providing both I/O and memory functions in a single closed-case removable expansion card. This increases the expansion functional density for portable computer hosts, such as PDAs. That is, it increases the amount of functionality that can be accommodated within a given volume allocation for expansion devices. In the second embodiment the removable memory is a private memory for application specific circuitry within the closed-case-removable expansion card. This enhances the utility of portable computer hosts, such as PDAs, as universal chassises for application specific uses.

Abstract: The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.

Abstract: A record and playback system for video images, especially suited for multi-camera Industrial surveillance. Techniques for acquiring multiple asynchronous camera inputs, compressing video images, and storing digital image data are described. Selective resolution recording improves object discernability without large large increase in data storage. A recording system with automatic data archive that eliminates the need for regular operator attention is disclosed.

Abstract: A record and playback system for video images, especially suited for multi-camera industrial surveillance. Techniques for acquiring multiple asynchronous camera inputs, compressing video images, and storing digital image data are described. Selective resolution recording improves object discernability without large large increase in data storage. A recording system with automatic data archive that eliminates the need for regular operator attention is disclosed.

Abstract: A Branch Prediction Cache (BPC) selects from among multiple branch address entries for a single return-type instruction that returns to multiple callers. The BPC has a branch address associative memory, a return address associative memory, and word line logic used to validate and qualify entries. The branch address associative memory monitors program addresses for previously stored branch addresses. The return address stack (RtnStack) stores the return addresses for the most recent call-type instructions. The top of the stack is input to the return address associative memory. When a program address has multiple matches in the branch address associative memory, the return address associative memory enables only the entry that has an associated return address matching the top of the RtnStack. In an alternate embodiment, the return address associative memory is combined with a branch address cache and target address associative memory.

Abstract: An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.

Abstract: A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a similar way: the low-order bits are computed with a conventional carry save adder (CSA) followed by a carry propagate adder (CPA), while the high-order bits are computed with an incrementer and selection logic. The first and second circuits are combined to form a third arithmetic circuit that takes four input operands, the first of which is wider than the other three, and speculatively computes two results: (1) the sum of the first and second input operands; and (2) the sum of the first, third, and fourth input operands. This combined circuit contains all of the elements of the first two circuits, but shares a single incrementer. A degenerate case of the third circuit occurs when the second and third inputs are common.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.