Abstract: A computer system preferably a mobile client computer, optimizes data handling and display through the use of predictive widgets. A predictive widget uses a predictive list of possible entries into a defined field of a form, as in a form filling application, to provide one or both of a predictive default entry for a field or a predictive fill once a user has started an entry into the field. A first predictive widget for a first data field interacts to determine the performance of a second predictive widget for a second field.

Abstract: A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus.

Abstract: A computer in which entry of data from an area provided on a display, touch screen or the like is accomplished by the provision of a "soft keyboard". Misentry of data is avoided by providing for the calculation of an offset as may be required by the entry habits of a user which target areas of a defined key cell spaced from the center of the cell.

Abstract: A personal computer is BIOS configured to boot from an installed CD-ROM storing multiple operating systems in different partitions of the medium. The computer is initially booted from a user selected or default partition emulating a logical drive. With the original boot partition maintained active, emulation of additional partitions as other drives is performed when needed. This is accomplished in BIOS with multiple device tables, each dynamically associated with a logical drive letter. Hence, the system files found in only the original boot partition remain available to the system when other logical drives are called.

Abstract: A method of user command or data acquisition in a processing system that allows for analysis of human hand and finger motions. The activities are then interpreted as operations on a physically non-existent input device. The resulting optical user/computer interface complements the visual screen-to-user path with a hand-to-image data acquisition link from the user to the processor unit. It allows for the emulation of different types of manually operated input devices (mouse, keyboard, etc.). Mechanical input units can be replaced by virtual devices, optimized for the current application and for the user's physiology. The speed, simplicity and avoidance of ambiguity of manual data input will be maintained. Sensing of finger motions can generate feedback to reduce the hazard of repetitive strain injury (RSI) syndrome.

Abstract: A computer having a riser card with a riser card interface that connects to an industry standard system board and has slots for expansion cards is provided with support circuitry that enables the computer system to perform personalized functions not provided for by the industry standard system board, including security functions. The placing of the support circuitry on the riser card allows the use of an industry standard system board and the personalization of the system to perform different IBM PS/2 functions depending on the installed riser card, in conjunction with Micro Channel and PCI bus architecture.

Abstract: Provides management tools for a System Owner to assure that a personal computer system is secured against access by an unauthorized user by foreclosing the possibility of circumventing system's security protection during an I/O ROM scan. The POST code is designed to prompt for the proper security password prior to allowing any adapter ROM utility to be run. An interrupt service routine will detect key strokes during adapter ROM scan and prior to passing control to the adapter ROM for handling of the keyboard interrupt. Prior to the ROM Scan for the system, the POST code detects whether or not C2 Security is enabled. On some systems, the C2 functionally may not be used and, the system does not consider password protection for the adapter Utilities. If however, the C2 functionality of the system is enabled, the POST code will continue to enable the password protection for the ROM Scan. Once the interrupt service routine is established the ROM scan will begin.

Abstract: A method and system for mapping a node topology is disclosed. The node topology is based on a computer system comprised of a high performance acyclic serial bus and a plurality of nodes coupled to the acyclic serial bus. Each node further includes an identification packet. The mapping topology establishes a root node based upon information found in each identification packet and establishes at least one branch node among the nodes based on the information. Next, the topology mapping method selects a first available branch node among the available branch nodes based on the information. The system then identifies any of the nodes that are child nodes to the first available branch node. Upon identifying all child nodes of the branch node, the system selects a next available branch node based upon the information. The processing continues until the root node is processed as a branch node.

Abstract: A keyboard bus is provided in a PC for connecting a peripheral such as a keyboard to a central unit, serially through external modules coupled to the bus enabling communication with the central unit by any of the external modules or the keyboard independently of other. The external modules are coupled serially to each other with a peripheral device, such as a keyboard, disposed most remotely from the central unit. The modules are serially connected in an open chain to the central processor for communication bidirectionally by an address signal to the intended respective module and an attention acknowledgment signal back to the central processor indicating a readiness for data reception.

Abstract: A SCSI computer system is provided whereby a host computer gains access to a targeted but non-local peripheral device, which device or devices are individually responsive to either SCSI or non-SCSI commands, by sending SCSI commands via a SCSI bus to a connected SCSI target computer which emulates the targeted peripheral device local to the SCSI target computer, whether the targeted peripheral device is responsive to only SCSI or only non-SCSI commands, to cause the targeted peripheral device to carry out the initial SCSI commands.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. The S/370 processors are alien to the S/88 Operating System, i.e., not in its configuration tables. Means are provided to isolate partner pairs of S/88 processors from the S/88 Operating System and couple the S/88 processors directly to corresponding pairs of S/370 processors for interaction therewith, transparent to the S/88 Operating System.

Abstract: A computing system with a SCSI controller includes SCSI transmission mode selection apparatus and method to switch the transmission line drivers between transmitting in SCSI 1, SCSI 2 or another mode. The controller selects a maximum data transmission rate compatible with each peripheral device connected to the controller. A user-defined option code is decoded by the controller to provide the user with control over transmission mode options for the drivers in the controller. Based on the data transmission rate and the selected option, the controller selects the SCSI transmission mode to use for each driver type, acknowledge line or data lines.

Abstract: In a computer operating a bootable CD-ROM or other bootable media having the capability of emulating one or more real drives, BIOS emulation parameters, such as drive number, memory partitioning and mapping are moved from BIOS and stored in a protected region of main memory. Upon a change of media, e.g., hard file, diskette, etc., as the computer undergoes a warm boot with new BIOS emulation parameters to enable DOS to process the change, the protected region of memory is not cleared. This preserves the BIOS emulation parameters which are restored to BIOS for the remainder of the boot sequence.

Abstract: A personal computer is BIOS configured to boot from an installed CD-ROM having at least one bootable partition. To enable swapping of large amounts of data stored on the CD-ROM at the BIOS level after the initial boot, the DOS-BIOS interface is modified so that a CD-ROM emulated as a hard drive file will emulate a floppy diskette image, a medium permitted by the operating system to be changed following an initial boot.

Abstract: A method and system for determining the maximum number of cable segments between all possible node to node paths on a high performance serial bus. The method for determining the maximum cable hops on the serial bus, which is acyclic and based upon the IEEE 1994 standard, consists of traversing a direct path between two nodes via the parent links. Further, the number of traversed paths is reduced from all possible node-to-node paths to only leaf-to-leaf node paths and leaf-to-root node paths for efficiently identifying the maximum number of cable segments between any two nodes within the serial bus.

Abstract: A computer system which includes a page mode memory in which a particular piece of data is accessed by first supplying a page or row address, then supplying a column address. These addresses are input to the memory by row address strobe (RAS) signals and column address strobe (CAS) signals. The RAS signals are determined by comparing input CPU addresses with row starting address information stored in registers, each of which corresponds to a memory socket in which a memory module may be installed. An algorithm is described for initializing the memory and its memory controller, including a determination of the starting address information.

Abstract: A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus.

Abstract: A system and method for generating a universal palette and for mapping the color space for an original image into the universal palette for compression. The universal palette utilizes a one byte three color format type allowing reservation of shades for a presentation layer of an operating system for the digital computer. The three color components for a pixel in an original image are then mapped to a specific palette having the one byte format. Mapping depends in part, upon the original component values. Where a color component does not correspond closely to a color component in the universal palette, it will have a value falling between first and second color values in the universal palette. The component is mapped to either the first or second color value on a pseudo-probablistic basis.

Abstract: A bus interface unit for passing data between an I/O bus and a system bus in a dual bus computer system is provided. The bus interface unit has incorporated therein an address listing and compare function to determine whether a requesting device on the I/O bus is to read data from or write data to an address on the system bus. If so, the bus interface unit allows passing of the data therethrough. If not, the system bus is relinquished and the requesting device writes to the address on the I/O bus. Also, compare logic is incorporated in the bus interface unit which decodes system bus addresses originated from a system bus controller such as the DMA, to determine whether the destination of the transfer is to system memory or the I/O bus.