Abstract: A CAM cell including three-transistor (3T) or four-transistor (4T) DRAM cells. Data is stored using intrinsic capacitance of each 3T or 4T DRAM cell, and is applied to the gate terminal of a pull-down transistor. Read operations are performed in the 3T and 4T DRAM cells without disturbing the stored data value by applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of a pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells.
Type:
Grant
Filed:
March 22, 2001
Date of Patent:
July 16, 2002
Assignee:
Integrated Devices Technology, Inc.
Inventors:
Chuen-Der Lien, Chau-Chin Wu, Ta-Ke Tien