Abstract: Call stack protection, including executing at least one application program on the one or more computer processors, including initializing threads of execution, each thread having a call stack, each call stack characterized by a separate guard area defining a maximum extent of the call stack, dispatching one of the threads of the process, including loading a guard area specification for the dispatched thread's call stack guard area from thread context storage into address comparison registers of a processor; determining by use of address comparison logic in dependence upon a guard area specification for the dispatched thread whether each access of memory by the dispatched thread is a precluded access of memory in the dispatched thread's call stack's guard area; and effecting by the address comparison logic an address comparison interrupt for each access of memory that is a precluded access of memory in the dispatched thread's guard area.

Abstract: Augmenting service oriented architecture (‘SOA’) governance maturity including receiving an evaluation of the maturity of the governance of the SOA; identifying, for each governance capability in dependence upon the evaluation of the maturity of the governance capability, one or more predefined risks to the SOA; establishing, for each governance capability in dependence upon the predefined risks to the SOA, a risk value representing the severity of the predefined risks; selecting, for each governance capability in dependence upon the evaluation of the maturity of the governance of the SOA and the predefined risk value, one or more governance work products; and communicating to predetermined stakeholders in the SOA the one or more predefined risks to the SOA identified for each governance capability, the risk value established for each governance capability, and the governance work products selected for each governance capability.

Abstract: Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.

Abstract: A computer chassis cooling sidecar for cooling one or more computers in a chassis of computers in a data center, the sidecar including an air intake chamber and a chassis delivery chamber, the air intake chamber having a first opening at a bottom end for receiving air from beneath the data center through perforated tiles in the floor of the data center located on the side of the computer chassis, the air intake chamber having at the top end a directional vane shaped to direct airflow from the side of the chassis to a chassis delivery chamber; wherein the chassis delivery chamber resides in front or back of the chassis and has an opening to receive air from the air intake chamber and an opening to deliver the received air to the front or back of the computer chassis.

Abstract: A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink.

Abstract: Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.

Abstract: Executing an accelerator application program in a hybrid computing environment with a host computer having a host computer architecture; an accelerator having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions; the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where executing an accelerator application program on an accelerator includes receiving, from a host application program on the host computer, operating information for an accelerator application program; designating a directory as a CWD for the accelerator application program, separate from any other CWDs of any other applications running on the accelerator; assigning, to the CWD, a name that is unique with respect to names of other CWDs of other applications in the computing environment; and starting the accelerator application program on the a

Abstract: Migrating virtual machines among networked servers, the servers coupled for data communications with a data communications network that includes a networking device, where migrating includes: establishing, by a virtual machine management module (‘VMMM’), one or more virtual machines on a particular server; querying, by the VMMM, the networking device for link statistics of a link coupling the network device to the particular server for data communications; determining, by the VMMM in dependence upon the link statistics, whether the link coupling the network device to the particular server is degrading; and if the link coupling the network device to the particular server is degrading, migrating a virtual machine executing on the particular server to a destination server. In some embodiments, migrating occurs is carried out only if non-degrading link is available. If no non-degrading links are available, the network device, rather than the link, may be failing.

Abstract: Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

Abstract: When a client apparatus receives a request for an electronic certificate from a server apparatus, the server apparatus reads a client certificate containing personal information and a server public key of the server apparatus from a storage unit and encrypts the client certificate using the server public key. The client apparatus also creates a temporary electronic certificate by setting, in a basic field of an electronic certificate, a predetermined item indicating that the electronic certificate is a temporary electronic certificate and by setting the client certificate having been encrypted in an extension field of the electronic certificate. Then, the client apparatus sends the temporary electronic certificate to the server apparatus.

Abstract: Methods, apparatus, and products for dynamically configuring current sharing and fault monitoring in redundant power supply modules for components of an electrically powered system, including summing, by a master service processor, during powered operation of the system, the present power requirements of components presently installed in the electrically powered system and setting, by the master service processor for each redundant power supply module in dependence upon the sum of the present power requirements, a current sharing tolerance and a fault reporting tolerance.

Abstract: A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.

Abstract: Migrating port-specific operating parameters during blade server failover including querying, by a system management server of a data center, a switch for port-specific operating parameters of a first port, the data center comprising blade servers coupled for data communications to one another and to the system management server by a network, the system management server comprising a computer subsystem that automates server management processes in the data center, the switch comprising a data communications component of the network, the switch comprising ports, the ports comprising physical points of connection between the switch and blade servers, each port having associated port-specific operating parameters, the switch connected at the first port to a failing blade server; and assigning, by the system management server, the port-specific operating parameters to a second port in a same switch or another switch connected at the second port to a replacement blade server.

Abstract: Methods, systems, and products are provided for code path tracking. Embodiments include identifying an instrumented trace point in software code to be path tracked; identifying a function executed at the instrumented trace point in the software code; identifying parameters for the function executed at the instrumented trace point; and recording a description of the function, the parameters, and the result of the execution of the function using the parameters.

Abstract: Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Abstract: Methods, systems, and products are disclosed for saving unsaved user process data in one or more logical partitions (‘LPARs’) of a computing system, the computing system having installed upon it a hypervisor for administering the LPARs, each LPAR supporting an operating system, each operating system supporting one or more user processes, that include: detecting, by the hypervisor, a predefined event that the hypervisor interprets as an indication that unsaved data of user processes for at least one LPAR should be saved; transmitting, by the hypervisor in response to detecting the predefined event, a save instruction to the operating system supported by the LPAR; and instructing, by the operating system in response to receiving the save instruction, each user process supported by the operating system to save any unsaved data.

Abstract: Administering offset voltage error in a current sensing circuit including recording by a power supply management module a current sensing voltage for a power supply when no operating load is drawn from the power supply and dynamically calculating by the power supply management module output current of the power supply with an active load in dependence upon the recorded current sensing voltage.

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract: Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.