Abstract: Systems and methods for the detection of motions of a pointed object upon a writing surface such as a touchpad are disclosed. The motions will be detected and converted in an analog-to-digital converter to digital codes representing the location of the pointed object upon the touchpad. The motion will be translated into a pen detect signal indicating the presence of the pointed object upon the touchpad. The digital codes will be filtered to minimize noise and formed into a filtered absolute coordinates digital code. The filtered absolute coordinate digital code and the pen detect signal will be converted to a touchpad-computer interface protocol and transferred to a computer system for further processing.

Abstract: Systems and methods for the detection of motions of a pointed object upon a writing surface such as a touchpad is disclosed. The motions will be detected and converted in a multiplexing analog-to-digital converter to digital codes representing the location of the pointed object and the pressure of the pointed object upon the touchpad. The location and the pressure will be translated into a pen detect signal indicating the presence of the pointed object upon the touchpad. The digital codes will be averaged to minimize noise created by vibrations and variations in the motions of the pointed object held by the human hand and formed into an absolute coordinate digital code. The absolute coordinate digital code, the pressure digital code, and the pen detect signal will be converted to a touchpad-computer interface protocol for transmission to a computer system for further processing.

Abstract: A method and means for the control of a cursor upon a display screen of a computer system by a pointed object such as a pen, stylus, or finger upon an electrical writing surface is disclosed. The method and means will allow the cursor to continue to scroll across the display screen in a fixed direction and at a fixed speed once the pointed object has transited from a workzone region to an edgezone region of the touchpad. Once the pointed object is in the edgezone region, the pointed object may be stopped. If a different direction or speed of movement of the cursor is desired, the pointed object can be moved in the new direction to establish the new direction and speed of movement of the cursor. The control of the cursor will return to the normal movement when the pointed object returns to the workzone from the edgezone.

Abstract: A semiconductor wafer packaging system to cushion semiconductor wafers from damage from shock and vibration during transportation is described. The semiconductor wafer packaging system has at least one a wafer case to enclose the semiconductor wafers. Each wafer case is placed within a wafer case padding unit. Each padding unit includes a rectangular cushioning block and a plurality of trapezoidal spacer blocks affixed to the four sides of the rectangular cushioning block. The rectangular cushioning block has an opening to accept the wafer case and a plurality of trapezoidal notches on two adjoining sides of the rectangular cushioning block. The wafer case padding unit is placed within a packaging canister for transportation.

Abstract: A three dimensional image detector is disclosed. The three dimensional image detector has a lensing system to focus incident light reflected from an object field upon a first and second image detector. The first and second image detectors are matrices of charge coupled devices. The first and second image detectors convert the incident light to electrical signals. The electrical signals from the first and second image detectors are converted in an analog to digital converter to a plurality of digital words that represent the magnitude of the light that impinges upon the first and second image detectors. The plurality of digital words are retained in a random access memory for processing within a digital signal processor. The digital signal processor will locate an object within the object field and determine the depth and contour information of the object and present this information with the plurality of digital words to external circuitry for further processing or display.

Abstract: A DRAM cell structure having charge amplification is disclosed. The DRAM cell has a capacitor to store an electrical charge. The DRAM cell further has a MOS transistor. The gate of the MOS transistor is coupled to a word line control to activate and deactivate the MOS transistor. The drain MOS transistor is coupled to one plate of the capacitor. The DRAM cell has a bipolar transistor to amplify the electrical charge stored on the capacitor. The bipolar transistor has a base that is the source for the MOS transistor. The base of the bipolar transistors is formed by masking and implanting a material of the first conductivity type adjacent to the gate to form the base. The collector of the bipolar transistor is the semiconductor substrate. The bipolar transistor has an emitter coupled to a bit-lines control which when activated will sense the charge amplified by the bipolar transistor.

Abstract: A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by connecting only one bit line within one sub-array to be connected to a sense amplifier, while the complementary bit line used for the reference voltage of the sense amplifier is selected from an adjacent sub-array, is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell.

Abstract: A method and structure for the evaluation of the density of charge induced to a semiconductor substrate during exposure to radiation as a result of integrated circuits processing procedures such as ion implantation and plasma etching is disclosed. A plurality of stacked gate field effect transistors, wherein each stacked has a charge collection capacitor attached to the gate, is fabricated on a semiconductor substrate. Each charge collection capacitor has an area that is different from every other charge collection capacitor. The to substrate is exposed to a radiation source. The threshold voltage for each of the stacked gate field effect transistors is measured. The difference in threshold voltage for the stacked gate transistors is proportional to the amount of charge induced during the exposure to the radiation and the density of the charge induced by the exposure to the radiation can be calculated from the comparison of the threshold voltage and the area of the charge collection capacitors.

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell.

Abstract: The present invention includes a parallel video format to field sequential video format conversion method wherein multiple analog signals that represent the magnitude of a set of colors that are components of the colors of a video display are converted to a set of digital video codes. This set of video codes buffered and rearranged to align with an input bus. The input bus is operably connected to a bus-exchange means which is operably coupled to a pair of Input/Output busses of two sets of dynamic random access memories. The Digital Video Codes are stored in sequence in the set of dynamic random access memories selected by the bus-exchange circuitry. The bus-exchange circuitry simultaneously selects the other set of the two sets of dynamic random access memories for connection to an Output Bus. The digital video codes are retrieved from the set of dynamic random access memories in a specific order by component color and placed on the output bus.

Abstract: A voltage reference circuit that will remain constant and independent of changes in the operating temperature that is correlated to the bandgap voltage of silicon is described. The voltage reference circuit will be incorporated within an integrated circuit and will minimize currents into the substrate. The bandgap voltage reference circuit has a bandgap voltage referenced generator that will generate a first referencing voltage having a first temperature coefficient, and a compensating voltage generator that will generate a second referencing voltage having a second temperature coefficient. The second temperature coefficient is approximately equal and of opposite sign to the first temperature coefficient. A voltage summing circuit will sum the first referencing voltage and the second referencing voltage to create the temperature independent voltage.

Abstract: A multiply/accumulate computation circuit is provided. The circuit will perform the multiplication of a first binary number that is a multiplicand and a second binary number that is a multiplier to produce a product. The product can be added or subtracted from a previous result. The product may be negated. The product may be multiplied by a factor of two. Or the product that is multiplied by the factor of two may be added or subtracted from the previous result. The multiplication is accomplished in a modified Radix 4 Booth's encoding and translation circuit to produce a set of partial products that are combined in a n operand adder to form a final result.

Abstract: A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type.