Abstract: A compound soft jaw for use in a machine vise has a replaceable jaw member into which the templates of the workpieces are cut. The compound soft jaw has a primary jaw member secured to a receiving plate of the machine vice. The first secondary jaw member is secured to the primary jaw member. The first secondary jaw member is machined to have a cutting template formed therein such that as the workpiece is secured within the machine vise, the workpiece is machined according to the template. Upon completion of machining of the workpiece, the first secondary jaw member is replaceable by a second secondary jaw member into which a second cutting template is formed. The primary jaw member has a height less than a height of the receiving plate. The secondary jaw member is placed on the primary jaw member and is forced into contact with a surface of the receiving. The secondary jaw member is then supported by the receiving plate, which prevents the secondary jaw member from movement during securing the workpiece.

Abstract: A levitating exercise wand and a method for use in therapy, exercise, and recreation is described. The method of use of a levitating exercise wand is to provide a therapeutic exercise subsequent to treatments of diseases such as lymphoma or during exercise therapy during treatment of concentration conditions such as attention deficit disorder. The levitating exercise wand has a rod having an attachment point such as a hole placed toward the upper end of the rod from the center of mass so as to maintain a vertical orientation when in motion. A string is attached to the rod and forms a closed loop. A first weight is placed at a lower end of the rod to transfer a center of gravity location. The first weight will allow the wand to have a more controlled motion rather than oscillating or vibrating in an uncontrolled fashion.

Abstract: A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

Abstract: An integrated circuit formed on a semiconductor substrate having multiple input/output signal paths such that the semiconductor substrate can be mounted to more than one package type. The integrated circuit formed on the semiconductor substrate has at least three pluralities of input output connector pads. The first plurality of input/output connector pads is placed on the semiconductor substrate and is attached to a first functional circuit of the integrated circuit. The second and third pluralities of input/output connector pads are placed on the semiconductor substrate and are attached to a second functional circuit of the integrated circuit. The third plurality of input/output connector pads is placed in an area separated from the first and second pluralities of input/output connector pads.

Abstract: A method of forming shallow trench isolation that reduces junction leakage at the boundary of shallow trench isolation and contact metallurgy of adjacent transistors and that avoids a reduction of carrier concentration in the source and drain region of transistors adjacent to the shallow trench isolation is described. The method to form a shallow trench isolation feature begins by providing a semiconductor substrate having a surface coated with at least one layer of an insulating material and a plurality of shallow trenches formed in the surface of the semiconductor substrate. A nitrogen doped insulating layer is then grown on the internal surfaces or sidewalls of the shallow trenches.

Abstract: A reference voltage generation circuit has a start-up circuit that will force the reference voltage generation circuit to assume a normal operation mode producing the desired reference voltage level and will reduce noise coupled from a power supply voltage source. The start-up circuit for reference voltage generation circuit will be disabled when a sensing circuit has determined that the reference voltage generation circuit has attained the desired reference voltage level.

Abstract: A current mode data communication system is disclosed. The current mode data communication system has a transmitter to simultaneously transmit two digital data bits. The two digital data bits are combined to form a current mode signal. The current mode signal has a first positive current, a second positive current, a first negative current and a first positive current. The current mode signal will be transmitted on a double bit current mode bus. Further the current mode communication system has a receiver coupled to the double bit current mode bus to receive the current mode signal and convert the current mode signal to a unextracted form of the two digital data bits. The output of the receiver is connected to a data extractor circuit extract the two digital data bits for the unextracted form of the two digital data bits.

Abstract: A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted a second integrated circuit chip to physically and electrically connect the first integrated circuit chip to the second integrated circuit chip.

Abstract: An interface buffer circuit connected at an interface of circuits having a high voltage power supply and circuits having a low voltage power supply, prevents damage due to application of the high voltage power supply to the output terminal of the interface buffer circuit. The interface buffer circuit has a predriver circuit and an interface buffer circuit. The interface buffer circuit has an interface buffer protection circuit. The interface buffer protection circuit consists of an inverter circuit. The inverter circuit has an input connected to the input of the interface driver circuit and an output connected to the gate of a MOS transistor. The source of the MOS transistor is connected to the predriver circuit to control the output of the predriver circuit. The interface buffer protection circuit further has a coupling capacitor connected to interface driver circuit.

Abstract: An edge triggered adjustable delay line circuit to determine the difference in time between a transition of a first signal and a transition of the second signal; a variably additive delay line circuit that will delay an input signal by a delay factor that is the sum of a multiplicity of variable delay factors; and a timing synchronization circuit to synchronize an internal timing signal with an external timing signal within one timing cycle is described. The timing synchronization circuit will utilize the edge triggered delay line and the variably additive delay line circuits to determine the synchronization parameters to synchronize the internal timing signal with the external timing signal.

Abstract: Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.

Abstract: The invention relates to a direct-type FIR filter, a method for calculating a scalar product in a FIR filter, and a method for designing a direct-type FIR filter. Successive words of a digital input signal are delayed in a delay line having delays (50A-50D) of the duration of one word, and the scalar product between the variously delayed words derived from the delay line and the corresponding constant coefficients is calculated. In accordance with the invention, calculation of the scalar product comprises a) combining the bits of words at the input (X0) and outputs (X1-X4) of the delay line bit by bit in a network of bit-serial subtractor and/or adder elements (51-56) wherein at least one of the bit-serial elements is involved in the multiplication operation of at least two different coefficients, and b) multiplying (49A-K) the multiplication results from the network by powers of two, and summing together (45-48) the results to yield the scalar product.

Abstract: An all-digital frequency synthesizing system that will eliminate spurious frequencies that degrade the overall performance of the generation of a binary waveform. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic reference counter. The periodic reference counter will count a number of periods of a periodic reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output signal will be toggled from logic level to another logic level. A new periodic output signal period can be chosen by selecting a new series of count integers in the count retention table. A count compiler will create the series of count integers retained in the count retention table.

Abstract: A dynamic threshold voltage MOSFET to provide increase drain-to-source saturation current (I.sub.DSsat) and lower off current (I.sub.off) is described. The dynamic threshold voltage MOSFET has a first diffusion-well of a material of a first conductivity type formed at the surface of the substrate to form a bulk region. A source region and a drain region of a material of a second conductivity type are diffused into the diffusion-well. A first gate is then placed on a first oxide surface above the substrate between the source and drain regions. An accumulated base bipolar transistor is then placed on the semiconductor substrate. The base of the accumulated base bipolar transistor is connected to the gate, the emitter is connected to the diffusion-well. A resistor is connected between the emitter of the accumulated base bipolar transistor and a substrate biasing voltage source.

Abstract: A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.

Abstract: A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.

Abstract: A method and system for issuing pen-input commands from a computer system to a controller for a touchpad to initialize the controller to the desired operating mode for the touchpad. The touchpad may emulate the function of a mouse pointing device or provide absolute coordinates of a pointed object such as human finger, a stylus, or a pen upon the touchpad.

Abstract: Systems and methods for the detection of motions of a pointed object upon a digitizing surface such as a touchpad is disclosed. The motions will be detected and converted to digital codes representing the absolute coordinates of the pointed objects upon the touchpad. The absolute coordinates will be translated into a stroke signal to interpret a single tap, a double tap, and a tap and drag of the pointed object on the touchpad. Further, multiple sets of absolute coordinates will be translated into a relative motion code that will contain the speed and direction of the pointed object as it is moved across the touchpad. The absolute coordinates will be interpreted by an autocursor controller to determine if the pointed object has transited between a workzone and an edgezone of the touchpad. If the pointed object is in the edgezone, a predefined relative motion code will be transmitted as an autocursor code.

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.