Patents Represented by Attorney, Agent or Law Firm Blackwell, Sanders, Peper, Martin, LLC
  • Patent number: 7255808
    Abstract: A phosphate ester-based functional fluid composition incorporating at least one erosion inhibitor selected from the erosion inhibitors of the invention. The phosphate ester-based functional fluids are particularly useful as aviation hydraulic fluids.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: August 14, 2007
    Assignee: Solutia, Inc.
    Inventors: David C. Silverman, Timothy K. Hirzel
  • Patent number: 6631456
    Abstract: A computer system (20) utilizes a monitor (24), keyboard (26), hard disk drive (28), processor (30), computer memory block (32), and memory based disk emulation device (22) to reduce access time for swap and paging files, thereby enhancing the computer system performance. The disk emulation device includes a device (22) manager (38) operable to select the number of logical drives, and a disk emulator (40) operable to cause actual memory devices (44-50) to appear as the virtual memory of the computer system disk drive (28). A memory controller (42) divides data bytes into data sets of two or four bits and saves the data sets simultaneously to the emulation memory devices (44-50). A backup battery (52) is provided to power the memory controller (42) and emulation memory devices (44-50) in the event of primary power supply failure.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: October 7, 2003
    Inventors: Lance Leighnor, Brian K. Spomer
  • Patent number: 6500741
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: December 31, 2002
    Assignee: Fabtech, Inc.
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Patent number: 6479885
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 12, 2002
    Assignee: Fabtech, Inc.
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Patent number: 6462393
    Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: October 8, 2002
    Assignee: FabTech, Inc.
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Patent number: D468322
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: January 7, 2003
    Assignee: nanonation Incorporated
    Inventors: Bradley K. Walker, John D. Turnipseed, Daniel J. Castagnoli