Abstract: A real-time scalable wireless switching network is described herein. In one embodiment, an exemplary network architecture includes, but is not limited to, a first access point coupled to a wired network, where the first access point is capable of communicating with one or more mobile nodes over a wireless network. The exemplary network architecture further includes a first node coupled to the wired network to communicate with the first access point over the wired network, where the first node includes a wireless network interface to wirelessly communicate with at least one of the first access point and the one or more mobile nodes over the wireless network. Other methods and apparatuses are also described.

Abstract: Techniques are disclosed to regulate an output of a power converter. One example power converter controller circuit includes a line sense input to be coupled to receive a signal representative of an input voltage of a power converter. A feedback input is included and is to be coupled to receive a feedback signal representative of an output of the power converter. A drive signal generator is included and is to generate a drive signal coupled to control switching of a switch to provide a regulated output parameter at the output of the power converter in response to the feedback signal. The drive signal generator is to latch the power converter into an off state in response to a detection of a loss of regulation of a power converter output parameter if the input voltage of the power converter is above a threshold level. The drive signal generator is to be unresponsive to the signal representative of the input voltage of the power converter while the power converter output parameter is in regulation.

Abstract: A logical data model is defined using a data-modeling framework. The data-modeling framework enables a user to define the logical data model using a series of graphical user interfaces (GUI) or an application-programming interface (API). The data-modeling framework dynamically translates the logical data model into a corresponding physical data model. The logical data model can be changed using the GUI or API and the physical data model is automatically adjusted to accommodate the changes to the logical data model. The logical data model extends capabilities of the physical data model and automatically allows these capabilities to be available to software developers using an application framework integrated with the data-modeling framework. The application framework enables the developer to configure various application features and data management operations using GUI or API.

Abstract: An embodiment of the present invention includes a range generator to simplify equivalence checking. A range generator is constructed. The range generator is represented by a characteristic function of a range of a cut function for a cut circuit in an implementation circuit and a reference circuit. The range generator is simpler than the cut circuit. Equivalence of the implementation circuit and the reference circuit is checked using the range generator.

Abstract: A Global Positioning System (GPS) receiver employs variable spacing of Doppler offset bins and code offset bins when acquiring a P(Y) code, to improve signal acquisition characteristics with respect to a search region having a plurality of Doppler offset bins and code offset bins. The receiver includes an acquisition module in which an input signal representative of a received P(Y) code is received and applied to a first programmable rate mixer. An output of the first programmable rate mixer is applied to a combiner, which selectively combines samples of the input signal based on a control input to dynamically determine the spacing of the code offset bins. An output of the combiner is normalized and applied to a correlation unit, which generates correlation measures of the received P(Y) code and a locally generated P(Y) code. A signal representative of the correlation measures is applied separately to each of a set of programmable rate mixers and mixed with separate mixing signals.

Abstract: The present invention relates to a multi-frequency display system and method for providing sharpness enhancement. The system comprises a sharpness enhancement circuit that is configured to receive a first and a second input video signal, where the first input video signal operates at a first frequency, and the second input video signal operates at a second frequency. The system further comprises a controller circuit coupled to the sharpness enhancement circuit, that is configured to generate a first sharpness enhancement signal corresponding to the first frequency and a second sharpness enhancement signal corresponding to the second frequency. The sharpness enhancement circuit generates a first control signal in response to the first input video signal and the first enhancement signal, and the sharpness enhancement circuit generates a second control signal based on the second input video signal and the second enhancement signal.

Abstract: An inductive/MR composite type thin film magnetic head which realizes high speed, high density recording while at the same time preventing the occurrence of read-out error by reducing NLTS.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable.

Abstract: A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment.