Abstract: A high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing. An inner gate member is formed on a p type substrate. A first source region and a first drain region are disposed in the p type substrate in alignment with the inner gate member for forming a lightly doped region. A conductive spacer is formed adjacent to and is coupled to each side of the inner gate member on the gate oxide layer for forming a gate member which overlaps the lightly doped region. A second source region and a second drain region are disposed in the first source region and first drain regions, respectively, self-aligned with the outer edges of the conductive spacers to form source and drain contact areas.