Abstract: A method and device for improved polycide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.
Type:
Grant
Filed:
March 25, 1999
Date of Patent:
February 13, 2001
Assignee:
Intel Corporation
Inventors:
Chia-Hong Jan, Julie A. Tsai, Simon Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating, Alan Myers
Inventors:
Carma Caughlan, Wei-Tong Sun, Suzanne Taylor, Mark Albrecht, Rick Feightner, Dave Heasty, Steve Brown, Steve Rodden, Pat Rodden, Son H. Lam, Bruce Clark, Kyle Fox, Bun Tan, Larry Altendorf, Greg Lento, Rob Armstrong, Todd Whitaker, Mike Midghall, Bob Eldridge