Abstract: Embodiments of this disclosure include a method and apparatus of dynamic spectrum allocation in coexisting heterogeneous wireless networks. A Mobile Station (MS) detects its own serving Access Point (AP) and a coexisting AP (cAP) of the serving AP, sends to the serving AP a service request message carrying a bandwidth demand and a cAP ID. The serving AP sends to a Dynamic Spectrum Allocation Module (DSAM) a spectrum request message carrying its own AP ID, the cAP ID and the spectrum demand. The DSAM allocates the spectrum dynamically using a dynamic spectrum allocation algorithm according to the spectrum demand, AP ID and cAP ID, and sends a spectrum allocation result to the serving AP, which allocates an appropriate bandwidth to the MS according to the spectrum allocation result. Thus, sharing spectrum dynamically between multiple coexisting wireless networks can be achieved, and spectrum utilization can be improved.

Abstract: A system and method for monitoring internal operation of a virtual machine (“VM”). The VM is operated to interpret and execute a program. During operation of the VM, status information regarding internal operation of the VM is stored to an internal memory buffer. The status information is subsequently extracted from the internal memory buffer during operation of the VM to monitor internal operation of the VM from a vantage point external to the VM.

Abstract: A method and apparatus for managing role based groups in a directory server is described. In one embodiment, a role attribute is defined for one or more entries in the directory server. A group of entries in the directory server is defined with a group role. The group role comprises one or more role attributes of one or more entries. The role attribute of the entries are queried to determine which entry possesses the group role. Entries that possess the group role are provided to the client.

Abstract: A layer-2 network switch device forwarding database implementation and method to access the forwarding database. A forwarding database (FDB) is implemented as a tree. A separate VLAN database is also structured as a tree. Each node in the tree represents a separate VLAN. For each VLAN, all associated ports are maintained in a data structure organized as a tree. Likewise, all port information is maintained in a tree-based data structure, and for each port, all VLAN information associated with the port is maintained in a tree data structure. Each node in a VLAN's port tree data structure is linked with each corresponding node in the port's VLAN tree data structure. Each pair of nodes maintains a linked list of all FDB entries relating to the node pair. Operations are quickly and efficiently performed on the FDB using the data structure architecture.

Abstract: Methods and apparatuses for maintaining customization information for an electronic device in an operating system independent component that may be accessed prior to completion of a boot up process to be used to provide customized functionality of the electronic device.

Abstract: Very small projections (10-2) are arranged on a mirror surface (10-1) of a mirror (10). The shape of a projection (10-2) is not limited to a circular cone, but it can be a hollow-cylindrical shape, semispherical shape, or square prism shape, and also, it can be a polyhedron with many faces. With a reduction in temperature of the mirror (10), water vapor contained in a gas to be measured condenses on the mirror surface (10-1) of the mirror (10). In this case, because of the very small projections (10-2) on the mirror surface (10-1), the condensation is promoted by the projections (10-2) serving as the cores. This facilitates condensation even at low dew points and improves response. Further, the size of condensation products does not easily vary relative to variation in flow speed of the gas to be measured, and this makes equilibrium of condensation less likely to break, increasing measurement accuracy.

Abstract: A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Abstract: A method for eliminating the flicker of a light source such as a florescent light having the first step of setting a first frame rate for the capture of a series of frames. Then, setting a capture integration period to a first integration period, and capturing a set of frames under an illumination source with a first frequency. Thereafter, determining the first frequency of the illumination by using a Fourier transform (FFT) of the set of captured frames. What is also disclosed is an apparatus for performing the above method having an image sensor and a capture control unit coupled to the image sensor.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.

Abstract: A method and apparatus to reduce conditional statements in normal code flow. A plurality of contiguous memory pages are allocated as either protected or unprotected. A pointer is defined to point to an address such that an operation (write or read) to an address in the unprotected page will occur when the conditional value is within an accepted range. The address is calculated by using a function of the conditional value as an offset to the pointer. When the conditional value enters the non-accepted or error range, the operation to the address of the pointer offset by the function of conditional value will fall within the allocated protected page. This will result in a faulting pointer and invocation of a signal handler which is independent of the normal code and only executed responsive to the conditional value entering an error range.

Abstract: Optical, opto-electronic or photonic component comprising, for a given operating wavelength, at least one optical cavity defined between two reflectors and confined laterally. The reflectors are of the phase change type and the area between the reflectors that corresponds to the optical cavity has a cut-off wavelength greater than the cut-off wavelength of the area surrounding it laterally, the operating wavelength lying between the two cut-off wavelengths. The method enables manufacture of a component of this kind using relatively shallow etching.

Abstract: A memory device is described. The memory device includes a memory array. An address buffer is provided for storing a plurality of bits of an address for addressing the memory array. The address is applied as an input of the address buffer. Each bit of the address can be in a first voltage state, a second voltage state, and a third voltage state. When at least one bit of the plurality of bits of the address is in the third voltage state, a test mode for the memory device is initiated. Circuitry is also provided for allowing the entire memory array to be addressed. The circuitry detects the state of two bits of the address and converts two corresponding address bits stored in the address buffer to the first voltage state if the two bits of the address are in the third voltage state. The circuitry is coupled to the address buffer. A method of triggering a memory device is also described.