Abstract: A method and apparatus for generating a display containing information about both the local and remote traffic handled by an integrated router/hub is provided. An integrated router/hub routes local messages between devices on a first local area network, and routes remote messages between the first local area network and a second local area network. The integrated router/hub stores a first set of values related to the local messages, and a second set of values related to the remote messages. A network management station executes a network management application the includes instructions which cause the network management station to generate a display of the information stored in the integrated router/hub. In response to user input, the network management station requests the information from the integrated router/hub, receives the information from the integrated router/hub, and generates the display of the information. The display may include charts that illustrate statistics derived from the information.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A method and apparatus for providing trace fault information to a trace fault handler. The trace fault information is evaluated prior to beginning execution of a micro code flow. The evaluated trace fault information is stored in a buffer and the micro code flow is executed. While the micro code flow is executing, if a micro code instruction of the micro code flow is executed that enables tracing, the trace fault information stored in the buffer is written to a data storage area. The data storage area is accessible to the trace fault handler.

Abstract: A control system. An apparatus having a motor; a host processor for generating a message containing motor control information; a control board for receiving the message and for transmitting a command, corresponding to the message, to the motor; and a communications medium coupling the host processor and the control board. The communications medium supports a first communications path and a second communications path. The first communications path is for transmitting messages from the host processor to the control board. The second communications path is for transmitting messages from the control board to the host processor.

Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Abstract: Circuitry which when combined with an EPROM in a single integrated circuit for connection to a microprocessor which provides suitable signals utilized by the additional circuitry to provude faster access to the code or data stored in the EPROM than can be accomplished without such additional circuitry by providing zero wait state burst performance. A state machine is utilized to manage the interface between the microprocessor and the burst EPROM.

Abstract: A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation. An inverse T-gate comprising a polysilicon upper member and a tungsten lower member is formed on a p type substrate. A gate insulating layer is formed between the composite gate and the p type substrate. A pair on n- source/drain regions are formed apart in the p type substrate in alignment with the sides of the polysilicon upper member for forming a lightly doped drain region. An oxide sidewall spacer is formed adjacent to each side of the polysilicon upper member on the tungsten lower gate member for forming a mask for a n+ source/drain implant. The n+ source/drain implant is made in the n- source/drain regions in alignment with the oxide sidewall spacers for providing a source and a drain for the transistor. The tungsten lower gate member improves the transistors performance and makes the transistor viable for VLSI manufacturing techniques.

Abstract: An acoustical lens for focusing ultrasonic energy having a transducer, a curved focussing lens and a voltage generator coupled with the transducer. The transducer is comprised of an array of piezoelectric crystal elements. The focussing lens has a concave upper surface and a planar bottom surface allowing the array of piezoelectric elements to be coupled to the bottomsurface of the array. The piezoelectric elements receive voltage from the voltage generator and transmit an energy ray through the focussing lens producing a focussed energy beam.