Abstract: A technique for self-servowriting a servopattern on a data storage medium is disclosed. An initial set of servopattern tracks is written by moving an actuator against a compliant structure (e.g., crashstop) with a first force applied thereto to hold the actuator in a first position to write a first track of the servopattern. The force is changed, thereby reaching a second position of the actuator against the compliant structure, at which a second track of the servopattern is written. The process is iterated for additional tracks. The distances (i.e., overlap) between pairs of written tracks are measured using a read element of the actuator, and this measured distance is compared to predetermined, desired distance. If the measured distance is within a specified tolerance, the process is complete; and if not, the tracks are erased and the process is repeated with changed forces applied to the actuator against the crashstop resulting in modified distances between tracks.

Abstract: A technique, including a method and associated system, for multitrack positioning during self-servowriting on a storage medium, and for controlling error growth as the servowriting steps across the storage medium. Readback amplitudes of multiple bursts from previously written tracks are combined using a parabolic interpolation relationship, for positioning when writing bursts on a subsequent track. This technique is especially useful for systems in which the read element is separated from the write element in the direction in which the servowriting steps across the medium. Also disclosed is an associated technique for controlling error growth, in which a reference waveform is derived and stored for use when writing subsequent tracks. The individual reference adjustments resultant from the multitrack positioning signal are combined in a weighted sum which controls error growth when the weights are calculated properly, as disclosed herein.

Abstract: A method and program product for managing membership of process groups of a distributed computing environment. Requests to alter membership of a first process group are received and presented to the first process group as a batched request. However, requests to change the membership of a second process group are received and presented to the second process group serially. Thus, the manner in which requests are presented can be different for various process groups. Additionally, different types of requests can be presented to the same process group in a differing manner. For instance, requests to join a process group can be presented as a batched request and requests to leave the process group can be presented serially, or vice versa.

Abstract: A system for managing membership of process groups of a distributed computing environment. Requests to alter membership of a first process group are received and presented to the first process group as a batched request. However, requests to change the membership of a second process group are received and presented to the second process group serially. Thus, the manner in which requests are presented can be different for various process groups. Additionally, different types of requests can be presented to the same process group in a differing manner. For instance, requests to join a process group can be presented as a batched request and requests to leave the process group can be presented serially, or vice versa.

Abstract: In order to efficiently execute a complex task within a computer system, the task is partitioned into a plurality of entities. A master process and a slave process are started for each entity. The master processes schedule operations to be performed, while the slave processes perform the operations. One slave process is coupled to one or more other slave processes because of path interconnections between the entities. Communication is established between any coupled slave processes such that one slave process may directly communicate with another slave process without involving the master processes. The master and slave processes execute in parallel on a plurality of processors.

Abstract: A new leader of a group of processors executing within a distributed computing environment is selected when the current group leader fails. The new group leader is selected from a membership list ordered in sequence of joins of processors to the group of processors. The selected leader is the next processor on the membership list after the failed group leader. In particular, it is the next active processor on the membership list. The group of processors is informed of the new group leader, after it is selected.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: In order to efficiently execute a complex task within a computer system, the task is partitioned into a plurality of entities. A master process and a slave process are started for each entity. The master processes schedule operations to be performed, while the slave processes perform the operations. One slave process is coupled to one or more other slave processes because of path interconnections between the entities. Communication is established between any coupled slave processes such that one slave process may directly communicate with another slave process without involving the master processes. The master and slave processes execute in parallel on a plurality of processors.

Abstract: A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a memory bus. The coupling facility includes a memory bus interface for the memory bus and a plurality of channels for coupling said channels to said processors. The memory bus interface includes an adapter with at least two hardware vectors provided for command detection, command isolation, and parallel testing of the error states of the intersystem channels, one which detects a command vector arrival, and a second which contains error state vector indicators. A LOCATE CHANNEL BUFFER (LCB) instruction is employed which performs a sense and reset operation on the command vector to identify and isolate a new command, and subsequently reads a vector of said error states vector indicator to determine the presence or absence of link errors.

Abstract: In a computer aided design system, a stored geometrical representation of a structure, the material properties thereof, and the loads imposed thereon are converted into a visualization of a mechanical quantity of the structure. A mesh is generated that describes the structure. By application of the finite element method to the mesh, the elements of a stiffness matrix, a loading vector and a vector including an associated degree of freedom index for each row and column of the stiffness matrix is generated. From the stiffness matrix and the loading vector, a matrix A and a right-hand side vector f are generated. A and f are related through the equation Ax=f, wherein the vector x represents the mechanical quantity at points of the mesh. A linear solver of the preconditioned conjugate gradient-type generates the elements of the vector x from A and f using a preconditioning matrix K.

Abstract: The syntactic definition of a grammar for language statements is the basis for a method for automatically generating error messages and error recovery for the language statements. The grammar is used to produce a parser, an error message generator, and error recovery for the language statements. The error message generator is produced automatically along with a parser and provides an indication of alternative valid input symbols. The method also produces the automatic generation of expected symbols lists to achieve error message generation goals. The error recovery routines are also produced automatically along with a parser and provide an indication of where valid parsing continues in the event of error detection in the language statements. The method also uses the dynamic generation of sets of synchronization symbols to achieve error recovery goals.

Abstract: The invention discloses a method and apparatus for solving a wide range of numerical problems that use N processing elements operating in parallel.To find the solution for a given problem relating to a given function function N points are selected in a determined interval wherein resides the solution. Such interval is known as the initial search interval and it is determined according to said given problem. Once the N points are selected the search interval is divided into smaller sub-intervals. The N processing elements are used to perform evaluations of the function at each of the N selected points, whereby the criteria for said evaluations are also determined according to said given problem. The results of the evaluations are used to determine the next search interval that is smaller than the previous one. The new search interval is divided into smaller parts in the same fashion as described above and further function evaluations are performed at given selected points.

Abstract: An implementation of one-to-many binary relations in an object-oriented database management system and object-oriented data model. The implementation includes storing all the information for the relationships of a relation contiguously inside the related instances, such as a source instance and a sink instance. The information stored within the related instances is used to create a doubly-linked ring of instances. The doubly-linked ring of instances is used in implementing a relation. In order to iterate through a relation, a cursor is employed. Encapsulated within the cursor are various pointers and data members which are used in cursing through the relation. The cursor is type safe and each cursor instance is maintained in a cursor dictionary, providing iteration safety. In addition, the cursor is operational in a forward direction and a backward direction, and the direction of the cursor can be dynamically switched.