Patents Represented by Attorney Blaney B. Harper
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Patent number: 5572236Abstract: This invention minimizes the number of non-trivial multiplications in the DCT process by rearranging the DCT process such that non-trivial multiplications are combined in a single process step. In particular, the DCT equations for the row-column application of the DCT process on k=pq points wherein p and q are relatively prime, are factored into a permutation matrix, a tensor product between matrices having p.times.p and q.times.q points, and a matrix whose product with an arbitrary vector having pq points requires pq-p-q+1 additions and/or subtractions. The tensor product is then further factored to remove non-trivial multiplications by developing a a first factor having (pq-p-q+1)/2 non-trivial multiplications and a diagonal matrix. The diagonal matrix is not unique for any set of data. Its j,j-th elements are chosen from a subproduct of the factorization of the tensor product. Once the diagonal matrix elements are chosen the remaining first factor is developed.Type: GrantFiled: November 12, 1993Date of Patent: November 5, 1996Assignee: International Business Machines CorporationInventors: Ephraim Feig, Elliot N. Linzer
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Patent number: 5179264Abstract: A solid state microwave generator is utilized as an excitation source for material/ plasma processes. The invention provides very close precise control of the solid state device's power levels to control the ultimate power output and frequency which control is not readily possible with vacuum tube devices. Utilizing the concepts of the invention the total power generated by the system may be easily varied and, further, the power may be easily monitored and used to control other device parameters such as frequency and the like. Because of the degree of control possible within the overall process system of the invention any measurable physical property of the process such as temperature, power, color (e.g., optical pyrometer), or the like that can be monitored and converted to a control signal can be utilized by the present system to carefully control the overall process conditions. These control features are lacking in currently available vacuum tube microwave devices.Type: GrantFiled: December 13, 1989Date of Patent: January 12, 1993Assignee: International Business Machines CorporationInventors: Jerome J. Cuomo, Charles R. Guarnieri, Stanley Whitehair
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Patent number: 5170226Abstract: Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted.Type: GrantFiled: May 17, 1991Date of Patent: December 8, 1992Assignee: International Business Machines CorporationInventors: Tadashi Fukuzawa, Hiro Munekata
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Patent number: 5121357Abstract: This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected memory cell by precharging all the bit lines of unselected memory cells associated with the word line of the selected cell. This is accomplished by switchably connecting a voltage source to all the unselected bit lines which charges their bit line capacitances. Then, when read current sources are switchably connected to both the selected and unselected memory cells and the associated word line is switched to a WORD SELECT source, the read current associated with the unselected bit lines flows via charging switches to the precharge voltage sources and the read current associated with the selected bit lines along with dynamic current from uncharged selected bit line capacitances flows into the selected cell.Type: GrantFiled: April 30, 1990Date of Patent: June 9, 1992Assignee: International Business Machines CorporationInventors: Siegfried K. Wiedmann, Dieter F. G. Wendel
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Patent number: 5117271Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.Type: GrantFiled: December 7, 1990Date of Patent: May 26, 1992Assignee: International Business Machines CorporationInventors: James H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Yuan-Chen Sun, Denny D. Tang
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Patent number: 5106767Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.Type: GrantFiled: April 10, 1991Date of Patent: April 21, 1992Assignee: International Business Machines CorporationInventors: Janes H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Yuan-Chen Sun, Denny D. Tang
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Patent number: 5098859Abstract: The control of barriers to carrier flow in a contact between a metal and a higher band gap semiconductor employing an intermediate lower band gap semiconductor with doping and greater than 1.5% lattice mismatch. A WSi metal contact of doped InAs on GaAs of 7.times.10.sup.-6 ohm/cm.sup.2 is provided.This is a continuation application of pending prior application Ser. No. 183,473, filed on Apr. 15, 1988 now abandoned which is a continuation of Ser. No. 876,063, filed on June 14, 1986, now abandoned.Type: GrantFiled: October 3, 1988Date of Patent: March 24, 1992Assignee: International Business Machines CorporationInventors: Thomas N. Jackson, Masanori Murakami, William H. Price, Sandip Tiwari, Jerry M. Woodall, Steven L. Wright