Patents Represented by Attorney Blayne D. Green

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  • Edge arrangements for integrated circuit chips
    Patent number: 7087452
    Abstract: A method is provided for forming microelectronic devices. This may include providing a wafer device having metallization layers, a plurality of integrated circuits and a channel area provided around each of the integrated circuits. Materials from within each channel area may be removed by etching or by laser to form an air gap around a perimeter of each integrated circuit. Each air gap may prevent cracking and/or delamination problems caused by a subsequent dicing of the wafer device by a wafer saw into a plurality of devices.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Subhash M. Joshi, Tom P. Leavy, Binny Arcot, Jun He
  • Pre-back-grind and underfill layer for bumped wafers and dies
    Patent number: 7071572
    Abstract: Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventor: Takashi Kumamoto
  • Photo-thermal induced diffusion
    Patent number: 7064063
    Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multilayered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, Daryl A. Sato
  • Circuit for enabling dual mode safe power-on sequencing
    Patent number: 7013396
    Abstract: A circuit that enables a safe power-on sequencing is described. The circuit enables a processor to be powered by an internal or external voltage source. The circuit detects for the presence of an external voltage regulator. If an external voltage generator is not providing a valid voltage source to the processor, the circuit enables an internal voltage regulator to provide a stable voltage source.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventor: Nazar Syed Haider
  • Method and apparatus to display video
    Patent number: 6928624
    Abstract: A method includes creating a first window to receive video which at least partially overlaps a second window on a region of overlap of the display. Pixels of the first window are set to a chroma color. Background pixels of the second window in the region of overlap are also set to the chroma color, The second window is configured to draw after the first window.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventor: Jim B. Estipona