Abstract: In a method for reducing electromagnetic interference in a clocked circuit, the clock circuit includes at least a first clock signal and a second clock signal. The method detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal. The second clock signal is delayed by a predetermined amount of time when the first transition is substantially aligned with the second transition.
Type:
Grant
Filed:
June 22, 2006
Date of Patent:
April 27, 2010
Assignee:
International Business Machines Corporation