Patents Represented by Attorney, Agent or Law Firm Booth & Wright, L.L.P.
  • Patent number: 6512333
    Abstract: The RF-powered plasma accelerator/homogenizer produces a quiescent plasma having a generally homogenous preselected plasma potential VPA and a space-charge neutralized plasma beam. The plasma accelerator/homogenizer includes an RF-conductive accelerator/homogenizer structure (17) having a plurality of dielectric-coated accelerator/homogenizer surfaces (619) with total surface area ARF and a containment assembly that includes an RF-grounded structure (112) with a total ground surface area AG, where ARF>AG. The accelerator/homogenizer structure is reactively coupled to an RF source using various approaches for direct or stray capacitive coupling (16).
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: January 28, 2003
    Inventor: Lee Chen
  • Patent number: 6429795
    Abstract: The present invention comprises a number transformer that includes an encoder that converts binary numbers to N-NARY numbers. Within an N-NARY number, exactly one of the bits has a value of one and all of the remaining bits have a value of zero. According to some aspects, several N-NARY numbers are generated in response to a binary number. A set of encoding instance selectors defines a partitioning of the bits of the binary number and a range of bits within each partition. The encoder then converts each subset of bits of the binary number to a corresponding N-NARY number, such that exactly one of the bits of each N-NARY number has a value of one and all of the remaining bits of the N-NARY number have a value of zero, and such that the one of the bits of each N-NARY number having a value of one is within the range of bits defined by the corresponding encoding instance selector. The set of encoding instance selectors may define a test point within a circuit under test, and may be produced by an on-chip ROM.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: August 6, 2002
    Assignee: Intrinsity, Inc.
    Inventor: Kenneth D. Amstutz
  • Patent number: 6404233
    Abstract: The present invention discloses an apparatus and method for determining the speed of a logic circuit relative to the clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to a transition detection circuit, which performs the OR/NOR function on the signals. In one embodiment the transition detection circuit comprises static logic. In another embodiment, the transition detection circuit comprises an N-NARY gate that performs the OR/NOR function.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: June 11, 2002
    Assignee: Intrinsity, Inc.
    Inventors: James S. Blomgren, Terence M. Potter
  • Patent number: 6367065
    Abstract: A design tool to support design of a N-NARY logic circuit is described. The designer develops a syntax statement that comprises encoded information according to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the N-NARY logic circuit and the specific configuration of transistors required to build the N-NARY logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the N-NARY circuit and a physical circuit description of the N-NARY circuit.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: April 2, 2002
    Assignee: Intrinsity, Inc.
    Inventors: Timothy S. Leight, Terence M. Potter, James S. Blomgren
  • Patent number: 6356316
    Abstract: Broadcast standard format video signals such as that adopted by the National Television Standards Committee (NTSC) or the European standard format of Phase Alternating Line (PAL) and some broadcast “compatible” video signals are used as inputs to a microkeyer to synchronize a microcomputer's display in a manner that allows full and complete merging of the two signals in the broadcast video domain by, for example, additive (mixing) or non-additive (keying) processes. The required synchronization in turn makes possible incorporation in any video space a variety of computer generated visuals such as illustrative graphics, titling and any other data displayed in the video. The merged video signal from this device may then be displayed on a television monitor, or transmitted, or received, or recorded by a video recorder or processed by a standard broadcast means for example. When applied to any common microcomputer display in its most fundamental form, no additional software is required.
    Type: Grant
    Filed: January 15, 1985
    Date of Patent: March 12, 2002
    Assignee: Video Associates Labs, Inc.
    Inventor: Henry B. Mistrot
  • Patent number: 6347327
    Abstract: The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry into the least significant dit, propagates into said dit. If so, the value of the dit is incremented. Otherwise, the dit value is output without modification. The present invention also generates a carry out signal if the increment control signal has propagated across all dits.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: February 12, 2002
    Assignee: Intrinsity, Inc.
    Inventors: Anthony M. Petro, James S. Blomgren
  • Patent number: 6345381
    Abstract: A design tool to support design of logic circuits is described. The designer develops a syntax statement that comprises encoded information to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the logic circuit and the specific configuration of transistors required to build the logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the logic circuit and a physical circuit description of the logic circuit.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: February 5, 2002
    Assignee: Intrinsity, Inc.
    Inventors: Timothy S. Leight, Terence M. Potter, James S. Blomgren
  • Patent number: 6334183
    Abstract: The present invention includes a partial register write handler. The write handler receives either two or three operands. An execution unit operates on portions of two operands, rather than on full operands. The result of the execution unit has fewer bits than an “additional” operand, which may be any of the two or three operands received by the write handler. An output multiplexer receives all of the bits of an execution unit result and selected bits of the additional operand, and produces an output that has as many bits as the additional operand. If the output of the multiplexer is a string of bits, the string of bits contains the execution unit result as a substring of bits. The remaining bits of the output of the multiplexer are selected from the additional operand.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: December 25, 2001
    Assignee: Intrinsity, Inc.
    Inventors: James S. Blomgren, Anthony M. Petro
  • Patent number: 6334136
    Abstract: The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result. If the intermediate result of the operation contains less bits than a full register, the intermediate result is “merged” with the second operand in that unaltered bits from the second operand are bypassed to the final result. Accordingly, the final result and the second operand have an equal number of bits.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: December 25, 2001
    Assignee: Intrinsity, Inc.
    Inventors: James S. Blomgren, Anthony M. Petro
  • Patent number: 6331701
    Abstract: The present invention discloses an RF-grounded sub-Debye neutralizer grid that is suitable for use in a plasma reactor and with a plasma beam. The grid comprises a grid core that is RF-grounded. The grid core comprises a plurality of grid holes. Each individual grid hole of the plurality of grid holes further comprises a sub-Debye hole where the diameter of said sub-Debye hole is smaller than the sheath thickness of the plasma and where the sub-Debye hole has a high aspect ratio. Additionally, an inner surface of each individual grid hole of the plurality of grid holes forms a natural ceramic in the presence of the plasma where the inner surface produces a surface neutralization by shallow angle elastic surface forward scattering.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: December 18, 2001
    Inventors: Lee Chen, Chen Yvonne
  • Patent number: 6324239
    Abstract: The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted into any vacated bit positions, and arithmetic shifts in which the value of the original most significant bit is shifted into any vacated bit positions. The present invention includes a general 32-bit shifter that can shift an arbitrary number of places in a single cycle, using any of the modes described above.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: November 27, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Terence M. Potter, James S. Blomgren, Anthony M. Petro
  • Patent number: 6301600
    Abstract: An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: October 9, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Anthony M. Petro, James S. Blomgren
  • Patent number: 6301597
    Abstract: An apparatus and method for performing saturating addition or subtraction on two signed or unsigned operands using N-NARY logic. The two operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries so that partitions may be saturated independently.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: October 9, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Anthony M. Petro, James S. Blomgren
  • Patent number: 6295622
    Abstract: The present invention comprises a number transformer that includes at least one updatable parameter, for example a ring counter, that produces an N-nary number. The N-nary number has several bits, exactly one of which has a value of one and the remaining of which have a value of zero. The number transformer also includes a masker, configured to perform a bitwise boolean AND upon the first updatable parameter and a binary number. The binary number is obtained from a linear finite state machine operating as a pseudorandom pattern generator. When several ring counters are included, multiplexers are added to select one of the ring counters. The multiplexers are controlled by a ROM, that iterates through the various test points in a circuit under test.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: September 25, 2001
    Assignee: Intrinsity, Inc.
    Inventor: Kenneth D. Amstutz
  • Patent number: 6289497
    Abstract: A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: September 11, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Timothy S. Leight, Terence M. Potter, James S. Blomgren
  • Patent number: 6288589
    Abstract: The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: September 11, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Terence M. Potter, James S. Blomgren, Anthony M. Petro, Stephen C. Horne
  • Patent number: 6275841
    Abstract: The described multiplier provides the signed or unsigned product of a multiplicand and multiplier represented in preferably 1-of-4 N-NARY signals by performing a preferably radix-four Booth recoding of the multiplier, producing partial products using a plurality of Booth multiplexers, summing the partial productsto produce two intermediate partial products using a six-level Wallace tree, and summing the two intermediate partial products using a carry lookahead adder. The Booth encoding is performed at the dit level using encoding circuitry implemented in N-NARY logic.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: August 14, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Terence M. Potter, James S. Blomgren, Anthony M. Petro
  • Patent number: 6275838
    Abstract: An enhanced floating point unit that supports floating point, integer, and graphics operations by combining the units into a single functional unit is disclosed. The enhanced floating point unit comprises a register file coupled to a plurality of bypass multiplexers. Coupled to the bypass multiplexers are an aligner and a multiplier. And, coupled to the multiplier is an adder that further couples to a normalizer/rounder unit. The normalizer/rounder unit may comprise a normalizer and a rounder coupled in series and or a parallel normalizer/rounder. The enhanced floating point unit supports both integer operations and graphics operations with one functional unit.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: August 14, 2001
    Assignee: Intrinsity, Inc.
    Inventors: James S. Blomgren, Terence M. Potter, Jeffrey S. Brooks
  • Patent number: 6271683
    Abstract: A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: August 7, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Stephen C. Horne, James S. Blomgren, Michael R. Seningen
  • Patent number: 6272653
    Abstract: The present invention comprises a method and apparatus for built-in self-test of logic circuitry for logic under test. The logic under test comprises a plurality of test points, each test point having a plurality of nodes. The test circuitry comprises a linear finite state machine. The linear finite state machine generates subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine. Moreover, the contents of the linear finite state machine are readable or writable via scan. The preferred implementation also comprises a test data bus coupled between the logic under test and the linear finite state machine. The test data bus is configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: August 7, 2001
    Assignee: Intrinsity, Inc.
    Inventor: Kenneth D. Amstutz