Abstract: The disclosure concerns asynchronous to synchronous synchronizers and particularly a technique which involves level shifting of a metastable voltage either within a synchronizer stage or between synchronizer stages. In a particular implementation of the invention, this level shifting is achieved by altering the relative proportions of at least one complementary pair of devices in a synchronizer or inserting diodes in order to shift the level of a metastable voltage outside the range of a fatal voltage window possessed or exhibited by an adjacent or following part or stage of the synchronizer. By this means, although the occurrence of a metastable condition cannot be avoided, the likelihood of propagation of the metastable condition throughout the synchronizer may be very significantly reduced.

Abstract: A computerized method of generating a truth table of a cell in a library of circuit cells includes representing basic elements of the cells in a hardware description language, representing each cell as a set of equations in that language and parsing the equations each in accordance with a respective abstract data tree of which the `leaves` or extremities are signal values or constants. The parsing of each equation yields a respective partial truth table. The partial truth tables are merged to provide a complete truth table, which is preferably subjected to Boolean and/or expression optimization to reduce the number of entries in the truth table.

Abstract: A method of automatic synthesis of a very large scale integrated circuit includes controlling the decomposition process in accordance with a reference order of inputs in a lexicographical expression of a Boolean function. The process improves the routability of the circuit by a reduction of complexity of wiring between cells of the circuit and external wiring to blocks connected to the synthesized circuit. The process also promotes an increase in speed and/or a decrease in area of the circuit, avoids ineffective decompostions which would be broken later during an optimization process and also helps to speed up the entire process of synthesis.

Abstract: A process of realizing large scale integrated circuits by means of a programmed data processor includes minimizing timing delays in the technology mapping phase by employing algorithms which are based on a linear model in terms of number of inputs and a load capacitance of a gating function and which permit a decomposition of the gating function into gates having m inputs and [(n-m)+1] inputs wherein m is greater than two. Balanced decompositions may be allowed in appropriate conditions.

Abstract: A compiler for a digital signal processor allows the designer to specify separately function, accuracy and throughput. The compiler employs a word structure having the signal attributes of bits, digits and subwords which all have a direct relationship to the size of the processor and throughput. From a budget of working bits and clock cycles implicit in the specification of accuracy and throughput the compiler is able to choose the optimal word structure for the application. The compiler can also propagate throughout an icon network, used for the specification of function, various estimation attributes such as word growth and quantisation noise, which allow the designer to observe the effect of design changes without recourse to simulation. A specific example of design employing a specified architecture and a specified computational grain is explained.

Abstract: A serial/parallel multiplier for the multiplication of a coefficient word with a data word of which the bits are broadcast n at a time where n is at least three. The structure comprises a plurality of pipes which where n is even each consists of a radix-4 encoder receiving two bits of the cluster and driving a partial product generator coupled to a respective carry-save array which forms the required two bits of the product by shifting and accumulation. For n equal to an odd number, the final sub-pipe consists of a radix-2 sub-pipe rather than a radix-4 sub-pipe and provides a single bit of the output, which consists of a cluster of n bits.

Abstract: A fractional bit-serial multiplier includes an array of partial product generators, an array of carry-save and accumulate stages and a spill-pipe to accommodate word growth and provide the higher order product terms. Circuitry between the carry-save stages and the spill pipe is provided to give the final partial products correct weighting and to avoid use of circuitry between the partial product generators and the carry-save stages.

Abstract: An architecture for a digital-to-analog converter or an analog-to-digital converter comprises a segmented voltage divider comprising a first resistive voltage divider providing a multiplicity of equal selectable voltage segments any one of which may be coupled directly across a second resistive voltage divider. The loading of the first resistive voltage divider by the second voltage divider is compensated by means of a controlled current source which responds to one of the voltage segments to provide a current which may be coupled by way of current mirrors in parallel with the second voltage divider.

Abstract: An incrementing subtractive circuit for use in digital signal processing is constituted by a full adder having data inputs of which at least one is inverted, a sum output, and a carry output which is coupled by way of a half adder circuit to a one bit upshifter at the carry input of the full adder. The one bit upshifter is controlled by a least significant bit control signal. The half adder includes a carry recirculation loop adapted to add a logical unity in response to the least significant bit control signal. The arrangement has the effect of adding integer two to the carry value of the full adder and achieves the additional incrementing necessary for the performance of incrementing subtraction or negating addition.

Abstract: A linear feedback shift register has two alternatively selectable feedback configurations enabling the shift register to produce either a pseudo-random state sequence or the reverse of that sequence. The shift register configuration may be characterized by a set of simple parameters and the register is thereby suitable for automatic synthesis.

Abstract: A digital to analog converter for the conversion of a digital signal into a corresponding analog signal. The converter has a resistive string comprising a string of first resistive segments having between segments selectable nodes including intermediate nodes wherein consecutive intermediate nodes are separated by a respective plurality of said segments. Switches provide selective coupling of at least one of the selectable nodes to an output. A decoder is responsive to the digital signal for controlling the switches. In order to reduce the output impedance of the converter and to reduce variation in the output impedance with the position of the selected node at least one auxiliary string of second resistive segments is coupled in parallel with the resistive string, providing between intermediate nodes substantially lower impedance than the respective first segments.