Patents Represented by Attorney, Agent or Law Firm Bracewell and Patterson
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Patent number: 6737894Abstract: An apparatus for generated impedance matched output signals for an integrated circuit is disclosed. The apparatus includes a master true driver circuit, a master complement driver circuit and multiple clone output driver circuits. The master true driver circuit includes a first driver control, a first output driver, a first impedance matching resistor and a first load. The master complement driver circuit includes a second driver control, a second output driver, a second impedance matching resistor and a second load. The clone output driver circuits, which are substantially identical to each other, can produce impedance matched output signals to their respective substantially identical loads. Each of the clone output driver circuit includes a driver control, a first unity gain amplifier, a second unity gain amplifier and a load. The inputs to the first and second unity gain amplifiers are supplied by the master true circuit and the master complement circuit via the driver control.Type: GrantFiled: May 1, 2003Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventor: James J. Covino
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Patent number: 6735759Abstract: A system, method, and program for providing language translators with contextual information for the text to be translated. The translator is presented with a graphical user interface in the base language, and can interactively translate each text label on the screen. Because the translation is performed on the text in the proper context, by editing the text withing the target application itself, the time and expense of Translation Verification Testing is reduced or eliminated. The ability to edit the text within the application is achieved by adding an editor function to the software application itself. Each text label in the application is stored in a localization file as a Java wrapper class component, which combines contextual information, such as the associated resource bundle name and key, with the text label itself. When the editor is activated, the translator can edit the text directly, and the contextual information is used to store the translation for later use.Type: GrantFiled: July 28, 1999Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Keiichi Yamamoto, Kin Hung Yu, David Bruce Kumhyr, Stanford Louis Yates
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Patent number: 6732673Abstract: An anchor system for flexible marker posts comprises an anchor that receives a post before the anchor is driven into the ground. In one version of the anchor system, a V-shaped configuration folded along two longitudinal side axes and one lower lateral axis. This version has front and rear plates, and the rear plate has and combines with two flanges to define a narrow pocket that receives the post. The post is secured in the pocket by deforming the pocket with punches. The anchor is retained in the earth by mechanical interference and friction. Additional embodiments include plates that are pre-bent into a V-shape, tabs for maintaining separation of the plates, and a one-piece anchor having a V-shaped lower portion and coplanar, horizontal, upper surfaces connected to the upper edges of the lower portion.Type: GrantFiled: February 3, 2003Date of Patent: May 11, 2004Assignee: Flexstake, Inc.Inventors: Robert K. Hughes, Sr., Robert K. Hughes, Jr.
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Patent number: 6734772Abstract: A transformer is provided along with a combination of bridging tap-changers to provide a wide range of selectable output voltages in discrete, relatively small voltage steps where the highest voltage is more than double the lowest output voltage. Relatively inexpensive, off-the-shelf, bridging tap-changers are utilized in conjunction with transformer winding schemes to provide a low winding loss ratio.Type: GrantFiled: January 11, 2001Date of Patent: May 11, 2004Inventor: Donald W. Owen
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Patent number: 6734872Abstract: A system, method, and program for optimally caching in a memory system an overlay instance. The system includes a local memory and a rasterizing processor coupled to the local memory. Responsive to receipt of a presentation requirement specifying an overlay stored in a memory device, the rasterizing processor determines whether an overlay instance for the overlay is cached in a memory system. Responsive to the overlay instance not being cached in the memory system, the rasterizing processor generates a new overlay instance for the overlay and caches the new overlay instance in the memory system. Responsive to the overlay instance being cached in the memory system, the rasterizing processor produces another overlay instance tailored to the presentation requirements, compares the another overlay instance to the cached overlay instance and then caches into the memory system only one overlay instance among the another overlay instance and the cached overlay instance that best presents the overlay.Type: GrantFiled: May 15, 2000Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: John Thomas Varga, Rose Ellen Visoski
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Patent number: 6734805Abstract: A section of pipe for well operations has a cylindrical fiber composite pipe body and a pair of metallic end fittings. The end fittings differ from each other in that they are provided with mating key features to ensure proper angular or rotational alignment between two abutting sections of pipe. Each pipe is also provided with an optical fiber for data transmission. A fiber optic coupling is located at each end of the optical fiber for sending and receiving data transmissions via optical signals. Multiple strings of pipe are abutted end to end to complete both mechanical and data interfaces. At the junction of each pair of adjacent pipes, the end fittings axially and rotationally align. The flanges of the end fittings are fastened together with bolts such that data transmission takes place between the optical fibers.Type: GrantFiled: August 3, 2001Date of Patent: May 11, 2004Assignee: ABB Vetco Gray Inc.Inventor: Ready J. Johnson
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Patent number: 6735719Abstract: A method for performing load testings on software applications is disclosed. A test script is initially recorded. A location at which dynamic data are first generated within the recorded test script is then identified. Proper data correlation statements are subsequently inserted into the recorded test script. The inserted data parameters are then substituted throughout the recorded test scripts. After verifying all dynamic data have been captured and replaced, a load test is performed on a software application utilizing the recorded test script.Type: GrantFiled: April 10, 2001Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Kevin LaVern Moe, Timothy Darold Vanderham
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Patent number: 6732980Abstract: A railway frog has a pair of wing rails with converging and diverging portions. A point member is located between forward portions of the wing rails. The forward portion of at least one of the rails has a section adjacent the point that has the rail head removed. A replaceable wear component having a head is located on an upper surface of the web of the wing rail. The wear component has a skirt that bolts to the flange of the wing rail. The wear component is formed of manganese steel.Type: GrantFiled: October 8, 2002Date of Patent: May 11, 2004Assignee: Progress Rail Services Corp.Inventor: Russell R. Hein
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Patent number: 6735635Abstract: A method and system for adjusting a message preamble on a shared bus, wherein the message preamble includes N synchronization characters, and each of the synchronization characters is separated in time by a random delay interval. First, an activity status is determined for the shared bus in terms of the number of stations that are currently active on the bus. The number of synchronization characters is then adjusted according to the bus activity status. The activity status is also utilized as a dynamic adjustment parameter for the random delay interval that includes a fixed delay term, D, added to a randomly determined delay increment, d. In this manner the message preamble specification is optimized according to real-time network demands, such that latency and data collisions are minimized.Type: GrantFiled: May 18, 2000Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: James William Feeney, Jorge R. Rodriquez, Edward Stanley Suffern, Robert William Bartoldus
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Patent number: 6732138Abstract: A method and system are disclosed for managing access to system resources by a user process within a multitasking data processing system. The data processing system includes a processor for executing kernel threads scheduled to the processor and a memory having a user address space which stores an application program and a kernel address space which stores an operating system kernel. The operating system kernel includes a kernel process comprising one or more first kernel threads which can each access the system resources. The user address space also stores a user process which has ownership of the system resources. The user process includes a second kernel thread comprising instructions within the application program. To access certain system resources, the second kernel thread invokes a first kernel thread within the user process.Type: GrantFiled: July 26, 1995Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Luke Matthew Browning, Jeffrey Scot Peek
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Patent number: 6732291Abstract: A method for providing a fault tolerant memory system having a number of memory arrays that includes at least one spare memory array and utilizing a data word organization of greater than 4 bits. The method includes detecting a multi-bit word error in a memory array. In an advantageous embodiment, a single package detect (SPD) logic, for detecting a package error of 1-4 bits, is utilized to identify the failed memory array. Next, the content of a first row of cells in the failed memory array is read and a first complement of the content is generated. Subsequently, the first complement is written back to the first row of cells in the failed array. A second read operation is then initiated to retrieve the first complement from the failed memory array, following which, a second complement of the first complement is generated. The second complement is then written to a corresponding first row of cells in the spare memory array and the method is repeated for all row of cells in the failed memory array.Type: GrantFiled: November 20, 2000Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Charles Arthur Kilmer, Shanker Singh
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Patent number: 6731110Abstract: A magneto-resistive device with built-in test structure. The magneto-resistive device includes a slider having first and second lower termination pads and first and second upper termination pads. A first conductive trace element electrically couples the first lower termination pad to the first upper termination pad and a second conductive trace element electrically couples the second lower termination pad to said second upper termination pad. The magneto-resistive device also includes a magneto-resistive transducer deposited on the slider and the resistance of the magneto-resistive transducer is obtained by passing an electrical current between the first and second lower termination pads and measuring a voltage across the first and second upper termination pads.Type: GrantFiled: May 28, 2002Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventor: Mark A. Church
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Patent number: 6732196Abstract: A method for dispatching input/output access requests to a direct access storage device (DASD) is disclosed. Each of a group of I/O access requests to DASD is assigned into one of at least two I/O access request categories, namely, high priority I/O access requests and low priority I/O access requests. Each of a group of I/O slots within DASD is assigned into one of at least two I/O slot categories, namely, high priority I/O slots and low priority I/O slots. An I/O access request from a first one of the two I/O access request categories is sent to any one of the I/O slots. An I/O access request from a second one of the two I/O access request categories is sent to only a slot belonging to a subset of the two I/O slot categories.Type: GrantFiled: February 26, 2002Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Abdo Esmail Abdo, Troy David Armstrong, Michael S. Faunce, Kurt Walter Pinnow
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Patent number: 6731129Abstract: An apparatus for measuring capacitance of a semiconductor device is disclosed. The apparatus includes a signal source circuit, a first transistor, a second transistor, and bypass capacitor. The first transistor is connected in series with the second transistor, and the second transistor is connected in series with a device under test. The bypass capacitor connected in parallel with the first and second transistors. Coupled to the first and second transistors, the signal source circuit generates a first signal and a second signal to alternately turn on said first and second transistors such that a discharge current is generated to flow through the first and second transistors.Type: GrantFiled: December 17, 2002Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Wendy Ann Belluomini, Chandler Todd McDowell, Sani Richard Nassif, Ying Liu
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Patent number: 6731996Abstract: A method of fabricating an article from a blank of material (e.g., aluminum alloy sheet) having anisotropic deformation properties, with tooling which has been designed by predicting flow and deformation of the blank using an analysis which decouples the anisotropic deformation properties of the blank. The method calculates the response of a small amount of the blank using crystal plasticity theory. The blank can be represented as a mesh having a plurality of elements. A strain path is predicted for each element using finite element analysis (FEA), and a stress-strain curve is defined for each element by performing a material point simulator (MPS) calculation for each element using its respective strain path. A second FEA is then carried out on the elements using the respective stress-strain curve for each element. The stress-strain curve for each element may be defined by assigning to each element a curve which lies between an upper bound curve and a lower bound curve, using various methods.Type: GrantFiled: October 19, 1999Date of Patent: May 4, 2004Assignee: Alcan International LimitedInventors: Stuart R. MacEwen, Pei-Dong Wu
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Patent number: 6731396Abstract: A registry is established in document presentation architecture that provides a unique numeric identifier for the most commonly used media types. Logic checks a print job and the accompanying form definition for a numeric identifier, a media name and a bin number in that order. Use of a numeric identifier eliminates ambiguity, caused by character matching that is utilized when using a media name identifier, between a request and printer media availability. Logic then attempts to find a matching numeric media identifier, a matching media name or a matching media bin in that order. If no matching identifier or name is found, the print server directs the media request to the default bin of the printer.Type: GrantFiled: December 14, 1999Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Roger Lee Buis, Reinhard Heinrich Hohensee, Susan Cheryl McElrafth, David Earl Stone, Nancy Elizabeth Wood
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Patent number: 6732232Abstract: A method, apparatus, and program product applicable within a multi-drive data storage system for adaptively allocating data reconstruction resources. In accordance with the method of the present invention, responsive to a detected drive failure, a resource allocation manager periodically determines the number of pending host system processing requests. The determined number of pending host system processing requests is then compared to a predetermined threshold value. Finally, a number of processing resources are allocated to data reconstruction in accordance with the results of the comparison of the number of pending host system processing requests to the predetermined threshold.Type: GrantFiled: November 26, 2001Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventor: Vikram Harakere Krishnamurthy
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Method and apparatus for verifying that instructions are pipelined in correct architectural sequence
Patent number: 6728872Abstract: A method and apparatus for enabling the correct architectural sequencing of fetched instructions prior to allowing the instructions to complete in the processor pipeline to reduce the occurrence of pipeline breaks. A branch processing unit (BPU) is designed to perform sequence checks for the addresses of all instructions fetched into the pipeline (i.e., both in-line and branch instructions) by the instruction fetch unit (IFU). A first instruction is fetched. The address of the next instruction in the architectural sequence is computed and stored within the BPU. The next instruction is fetched and its address is compared to the next instruction address stored in BPU to determine if it is the correct address. If the next instruction address matches that of the architectural sequence, the instruction is permitted to “live” (i.e., continue through to completion). When the address does not match, the instruction is killed (i.e., not allowed to complete) and a new instruction is fetched by the IFU.Type: GrantFiled: February 4, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Brian King Flacks, Harm Peter Hofstee -
Patent number: 6728818Abstract: An Input/Output (I/O) adapter for use with a second I/O adapter in a clustered configuration. The I/O adapter includes a dedicated communication link, such as a high-speed serial bus, that provides for communication between the I/O adapter and the second I/O adapter. The I/O adapter also includes a message passing circuit, coupled to the dedicated communication link, that allows for transferring of data between the I/O adapter and the second I/O adapter. The I/O adapter further includes a doorbell circuit, coupled to the message passing circuit, that generates interrupts to provide a low level communication between the I/O adapter and the second I/O adapter. A mirroring directory, coupled to the message passing circuit, is also included in the I/O adapter to provide for the mirroring of cache directory writes.Type: GrantFiled: June 27, 2001Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Brian Eric Bakke, Robert Edward Galbraith, Frederic Lawrence Huss, Daniel Frank Moertl, Paul Gary Reuland, Timothy Jerry Schimke
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Patent number: 6727921Abstract: The present invention provides an improved graphical user interface (GUI) component for presenting mixed mode inputs. A GUI component disclosed as a mixed mode input box according to the present invention permits easier selection within the GUI component of an input among mixed mode inputs such as numeric inputs within a numeric range and combined textual and numeric inputs. Pull-down menu is activated to allow the user to select among mixed mode inputs. When the user selects a numeric value within a numeric range only as the selected input, scroll buttons are activated and used by the user to increment or decrement the numeric value to a desired, selected input value. When the selected input is any other input, such as a combined textual and numeric input, scroll buttons are de-activated. Display of mixed mode input box occupies a relatively small display area and only requires a relatively small amount of code to provide such a layout.Type: GrantFiled: March 20, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventor: Farzad Mirshah Valad