Abstract: A receiver processor for use in a SONET OC-48 or SDH test or network environment. The processor includes a 16:32 demultiplexer, descrambler, and a cross-connect enabling individual STS-3s in the incoming signal to be routed to selected STS-3s in the outgoing signal. An overhead and data capture function enables overhead and data bytes to be captured from each frame.

Abstract: A multi-chip module development substrate (12) contains embedded test circuitry (30). Vias (38) connect I/O channels (Cn) of the test circuitry with conductive runs in interconnect layers (16,18) that are part of an interconnect structure (17) of the development substrate. Integrated circuit chips (14) are then mounted on the multi-chip module development substrate in selected electrical contact with the conductive runs. The embedded test circuitry includes multiple timing analyzer circuits (TAn) and multiple analog probe circuits en). In a preferred embodiment, these timing analyzer circuits and analog probe circuits are provided in redundant pairs, with a pair of each associated with each of the I/O channels. Multiple pairs of each kind of circuit are grouped within test cells (70) physically arranged in rectangular areas. Adjacent test circuit cells may be rotated with respect to each other to achieve more efficient connections to interconnect structure.

Abstract: An inline filter having a swivel right-angle fitting for coupling an inlet or outlet tube. The fitting includes a stem having a pair of O-rings and a distal ridge and notch. The cap of the filter includes a port having a plurality of annular, resilient tabs that engage the notch and ridge to retain the fitting to the cap.

Abstract: A trigger system for a digital oscilloscope operating in external clock mode. Every n pulses, the trigger system generates a trigger signal. The trigger system therefore provides a trigger every n samples of the input signal waveform.

Abstract: A high-speed data acquisition and processing system. The system includes a sequential sampler that samples an input signal at periodic intervals. The resulting samples are provided on a plurality of sample outputs. These sample outputs are received by a matrix of signal processors, each of which receives and processes at least two inputs, and provides a processor output. The first row of signal processors receives the sample outputs and processes them. Subsequent rows of signal processors receive and process the outputs of signal processors in previous rows.

Abstract: A cellular phone has, in addition to an antenna, speaker and microphone, a device interface capable of transmitting electronic information between the cellular phone and an electronic device, such as a computer or modem, when the device is physically connected to the cellular phone. The cellular phone also has a battery pack. The battery pack has, in addition to a battery for powering the cellular phone, an infrared port for transmitting infrared information between the cellular phone and an electronic device with infrared capability. The infrared port is connected to an infrared converter, which is connected to the device interface. The infrared converter converts electronic information to infrared information for transmission between the cellular phone and the device over the infrared port.

Abstract: A method of sending acquired graphical data over an alphanumeric paging service. The data is compressed, split into and blocks of a size which the paging service can handle, and transferred to the paging service. The paging service transmits the data to a wireless receiver attached to a computer. The computer displays the information on its display, and can further process the data.

Abstract: A defibrillator patient circuit including a capacitor having a two terminals; a first relay having a common terminal, and two contact terminals, where the first relay's common terminal is connected to the capacitor's first terminal; a charger circuit having two terminals, where the charger circuit's first terminal is connected to the first relay's first contact terminal and where the charger circuit's second terminal is connected to the capacitor's second terminal; a second relay having a common terminal, and two contact terminals, where the relay's second contact terminal is connected to the capacitor's second terminal; a first defibrillation contact connected to the second relay's common terminal; a second defibrillation contact connected to the first relay's second switch contact; and an inductor connected in series with the capacitor, the two relays, and the two defibrillation contacts.

Abstract: A defibfillator has a self healing storage capacitor connected in parallel with a safety resistor, and a microcontroller. Upon receipt of a calibration request, the microcontroller charges the capacitor to a charging voltage greater than a starting voltage, then discharges the capacitor through the safety resistor. As the capacitor is discharging, the microcontroller continuously measures the voltage across the capacitor. When the microcontroller detects that the voltage across the capacitor is less than or equal to a starting voltage, a timer in the microcontroller is started. When the microcontroller detects that the voltage across the capacitor is less than or equal to an ending voltage, the timer in the microcontroller is stopped. The microcontroller then determines an elapsed time between the time the timer was started and stopped. The microcontroller then calculates a capacitance value of the capacitor based on the starting voltage, the ending voltage, and the elapsed time.

Abstract: A high-accuracy QRS detector detects "activity" on the ECG waveform. Activity results from a steep slope of one sense followed shortly thereafter by a steep slope of the opposite sense. Low-pass filtering activity and multiplying by 2.5 yields a noise threshold. An activity peak which rises above this threshold may be a QRS complex. The detector waits three-fourths the average R to R interval after detecting a peak to allow for greater peaks to be detected. If none are, the peak is confirmed if it is either at least half the magnitude of the previous peak, or if it occurs at least three-fourths the average R to R interval after the last detected peak. This high-accuracy detector may be coupled with a fast QRS detector by providing it with the peak values of the previous three detections. The fast detector will detect if the slope is greater than three-fourths the average of the previous three detections, greater than the noise threshold, and more than 160 ms has elapsed since its last detection.

Abstract: Method and apparatus for removing baseline wander from an ECG signal. The ECG signal is filtered with a high-pass filter having a variable corner frequency. In response to finding low-frequency components in the output of the high-pass filter, its corner frequency is temporarily increased. The corner frequency may decrease according to a decay function or sensing the absence of a low-frequency component in the filter's output. The corner frequency may be decreased in response to sensing ECG activity.