Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.

Abstract: In accordance with the present invention, there is provided a method by which narrow lateral dimensioned microelectronic structures can be formed using low temperature processes. An uncured resist layer (e.g. PMMA 42) is deposited on a supporting layer (e.g. silicon 40) and patterned. Then, by using an isotropic process such as a low temperature chemical vapor deposition, a conformal layer (e.g. silicon oxynitride 44) is deposited substantially evenly on the vertical walls and on the horizontal surfaces of the uncured resist layer. An anisotropic etch such as reactive ion etching is then used to substantially remove the conformal layer from the horizontal surfaces without substantially etching the conformal layer from the vertical walls of the resist. The resist can then be selectively removed, producing isolated vertical sidewall structures (e.g. silicon oxynitride 46) which could be used, for example, as a negative tone mask. Alternatively, instead of removing the resist, another resist layer (e.g.

Abstract: An electrostatic decontamination method and decontamination device (10) is disclosed for decontaminating the surface of a semiconductor substrate. The decontamination device (10) includes particle ionizing device (24) that charges contaminating particles (26) on the surface of semiconductor substrate (16) thereby creating ionized particles. Decontamination device (10) also includes substrate biasing device (12) for creating a charge accumulation layer (14) at the top of semiconductor substrate (16) so that the charge accumulation layer (14) has the same charge sign as the ionized particles. In addition, the invention analytically characterizes particles using contaminating particle isolator (44) which contains a particle ionizing device (24) that charges contaminating particles (26) on the surface of semiconductor substrate (16) thereby creating ionized particles.

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).