Abstract: Multiple memory arrays (215, 225) in embedded applications are each tightly coupled to their own Built-In Self-Test (BIST) controller to form BISTed memory cells (210, 220) supporting structural and retention testing. Testing on multiple BISTed memories (210, 220) is initiated by common INVOKE (230), RETENTION (240), and RELEASE (250) signals. DONE and HOLD signals are combined (260, 280) from the multiple BISTed memories (210, 220) and delayed to generate a global "all memory" DONE (265) and HOLD (285) signals. FAIL signals are combined (270) from the multiple BISTed memories (210, 220) to generate a global "any memory" FAIL (275) signal. The BISTed memories can be combined in multiple stages to meet power limitations.

Abstract: A data processing system (100) of the present invention analyses input data (10) for statistical similarities in time and determines processing steps depending on the analysis. The system (100) transfers a first data set (12) which changes at every time transition (i-1) to i into a second data set (13) to output sets (22 and 23) by a transfer function H. According to a method of the present invention, the number of calculation instructions h(n) which are performed is established by comparing consecutive old input data (12) and new input data (13). The transfer function H is thereby simplified and the number of executed instructions optimized.

Abstract: Data is allocated into multiple memories with selective variable replication for maximizing performance by minimizing concurrent memory access conflicts. Requirements for concurrent access are summarized in a transformed concurrent access graph. Graph vertices are merged to disallow variable replication. All potential graph merges that cause a reduction in machine cycle time are identified. The ratios of saved cycles/memory cost in bytes are then computed for each potential merge. The potential merges are then sorted by their saved cycles/bytes ratio. Finally, potential merges resulting in replicated variables are selected based on their cycles/bytes ratios until a predefined memory target size is achieved. Either graph coloring or clique partitioning can be used to allocate variables into memory banks.

Abstract: A sigma delta modulator (10) for use in codec applications provides dynamic range adjustment and avoids asymmetrical signal clipping. The modulator (10) has a summing circuit that sums a plurality of inputs, one of which is a dither component. The dither is programmably modifiable to provide enhanced performance. The dither is provided by a pseudo random number generator (100). The pseudo random number generator (100) has an n-bit shift register (106) coupled to a last code detect (108) to detect the end of a pseudo random number sequence. At that time, a new preset code can be loaded (110) into the shift register (106) to provide different dither characteristics. This allows the pseudo random number generator (100) to programmably determine the percentage of ones and zeros to add to the output signal. The dither output can be inverted (104) to shift the dither up or down.