Abstract: A circuit for driving capacitive loads in a highly efficient manner. In one embodiment, a drive portion is connected to at least one end of a capacitive electric load being applied a voltage waveform. The embodiment further comprises a switching circuit portion having its output connected to the above one end of the capacitive load in order to supply a fraction of the overall current demanded by the load. Additionally, a switching circuit and accompanying switching method provide for efficiently supplying peak current to the capacitive load during voltage fluctuation in the voltage waveform. Briefly, the invention is a circuit arrangement aimed at providing a highly efficient drive for the capacitive load, using a combined linear/switching setup and without distorting the quality of the waveform generated across the capacitive load.

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value ‘K’ connected to the input of a programmable counter means that is configured for a count value of ‘K’ or ‘K+1’ depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract: A circuit controls the gain of an amplifier that amplifies an information signal. The circuit includes a buffer that stores two samples of the amplified information signal, and includes a gain-determination circuit coupled to the buffer. The gain-determination circuit generates a gain adjustment that is based on the two samples and that causes the amplifier to shift the amplitude of the amplified information signal to or toward a predetermined amplitude. Such a circuit can provide an initial, coarse gain adjustment to a read-signal amplifier in a disk-drive read channel. Compared to prior read channels, this initial adjustment promotes faster settling of the amplifier gain at the beginning of a data sector. This faster settling allows the data sector to have a shorter preamble, and thus allows the disk to have a higher data-storage density.

Abstract: A circuit includes a buffer for receiving and storing two samples of a signal, and a phase calculation circuit for calculating from the samples a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery loop reduces the overall alignment-acquisition time.

Abstract: A sigma-delta-type converter comprises: a sigma-delta modulator having a digital output having a first prefixed bit number; a randomizer including a circular memory; an analogical reconstruction filter comprising a branch number equal to said first default number including sampling capacitors and a low-pass filter; characterized in that said circular memory comprises a number of elements equal to said first default number of bits less one and receives in input said first default number of bits less one, and in that a bit of said first default number of bits is applied to one of said branches of said reconstruction filter.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: A memory device implements a reading operation. The memory device includes first, second, and third memory cells; a read circuit coupled to the memory cells and operable to read first, second, and third values, respectively, from the first, second, and third memory cells; and a comparison circuit coupled to the read circuit and operable to compare the first and second values with fourth and fifth predetermined values and to generate a data-valid signal that indicates that the third value is valid if the first and second values equal the fourth and fifth values, respectively. The memory device may further include a selection circuit coupled to the read circuit and to the comparison circuit and operable to couple the third value to a data bus in response to the data-valid signal.

Abstract: A Viterbi detector receives a signal that represents a sequence of values. The detector recovers the sequence from the signal by identifying surviving paths of potential sequence values and periodically eliminating the identified surviving paths having a predetermined parity. By recognizing the parity of portions of a data sequence, such a Viterbi detector more accurately recovers data from a read signal having a reduced SNR and thus allows an increase in the storage density of a disk drive's storage disk. Specifically, the Viterbi detector recovers only sequence portions having a recognized parity such as even parity and disregards sequence portions having unrecognized parities. If one encodes these sequence portions such that the disk stores them having the recognized parity, then an erroneously read word is more likely to have an unrecognized parity than it is to have the recognized parity.

Abstract: A Viterbi detector receives a signal that represents a binary sequence having groups of no more and no fewer than a predetermined number of consecutive bits each having a first logic level, where the groups are separated from each other by respective bits having a second logic level. The Viterbi detector recovers the binary sequence from the signal by calculating a respective path metric for each of no more than four possible states of the binary sequence, and determining a surviving path from the calculated path metrics, where the binary sequence lies along the surviving path. Or, the Viterbi detector recovers the binary sequence from the signal by calculating respective path metrics for possible states of the binary sequence, calculating multiple path metrics for no more than one of the possible states, and determining the surviving path from the calculated path metrics.

Abstract: A system and method of advancing the commutation sequence of a brushless DC motor is provided. The motor having a plurality of coils, each of the coils coupled together at one end to a common center tap and coupled at an opposite end, through a respective coil tap, to both a source voltage and ground via selectively actuateable switches having diodes coupled in parallel therewith. The motor operates in a pulse width modulation (PWM) mode having PWM-on states and PWM-off states. During PWM-off states, a coil tap voltage from the coil tap of a floating phase is provided to a preconditioning circuit. The preconditioning circuit adjusts the floating phase coil tap voltage to compensate for an amount of voltage substantially equal to an amount of voltage by which a voltage at the center tap deviates from zero. The preconditioning circuit further includes sharpening circuitry for amplifying the adjusted floating phase coil tap voltage.

Abstract: A synchronizer circuit includes an input terminal, an output terminal, and a recovery circuit coupled to the input and output terminals. The input terminal receives an input signal that includes a sync mark, and the recovery circuit is operable to recover the sync mark from the input signal and to generate a synchronization signal on the output terminal in response to the recovered synchronization mark. For example, such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a Viterbi detector that is separate from the circuit. By performing the sync-recovery function in a separate circuit, one can reduce the complexity and increase the data-recovery speed of the Viterbi detector. Furthermore, the synchronizer circuit can recover the sync mark by executing state-transition routines in alignment with the input signal. For example, one can align the synchronizer circuit's state-transition routines to the preamble of the read signal.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: An apparatus and method for switching between two power supplies, a primary power supply and a secondary power supply. The present invention generates a first reference voltage using the voltage of the primary power supply and the secondary power supply, wherein the primary power supply voltage is variable. The present invention also generates a second reference voltage based on the voltage of the primary power supply. The first and second reference voltages each have a different slope and the crossing point between these two reference voltages indicate that a switch between the primary power supply and the secondary power supply should occur.

Abstract: Regulation of the output voltage of a power supply employing a flyback-type self-oscillating DC—DC converter employing a transformer. The primary winding circuit of the transformer senses a current recirculation loop for discharging the energy cyclically stored in an auxiliary winding of the self-oscillation loop of the converter such as to represent a replica of the circuit of the secondary winding of the transformer and by summing a signal representative of the level of the energy stored in the auxiliary winding with a drive signal on a control node of a driver of the power switch of the converter.

Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.

Abstract: An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.

Abstract: A circuit for limitation of maximum current delivered by a power transistor comprises: a network for detection of the current delivered by the power transistor which generates a first electrical signal; a reference network for generating a reference current proportional to a resistor and self-limited, provided by means of a current generator circuit and a limiting circuit with current mirror; and an operational amplifier which compares the first electrical signal with the reference current and which tends to inhibit the power transistor if the current delivered exceeds a certain threshold value.