Abstract: The response time of an automated optical disk library is improved by writing object delete requests to a deleted objects table before actually physically deleting those objects. By collecting object delete requests in a list of pending deletes for each volume in the library the number of necessary mounts are reduced. The delete requests in a list of pending deletes for a given volume are physically deleted just prior to performing a write or defrag request for that volume. The list of pending deletes for that volume are then deleted from the deleted objects table. During idle periods a predetermined number of pending delete requests will be performed for the currently mounted volume. If there are no pending delete requests for the currently mounted volume then a predetermined number of pending delete requests will be performed on the opposite side of the currently mounted volume.

Abstract: The invention is a magnetic tape subsystem in which dropout can be controllably simulated. Such simulation is accomplished by inserting an electronic filter between the read transducer and a recording channel detector of the magnetic tape subsystem. The filter scales a spacing loss transfer function from a spatial domain to a frequency domain. After selecting an appropriate head-tape spacing, the frequency domain transfer function is computed and the filter is designed. Upon insertion of the filter, dropout is then simulated. Such simulation allows for an assessment of recording channel operation with a particular amount of dropout, including the margin to failure of magnetic tape heads or other components. Because the filter is completely electronic, dropout simulation can be performed in the field for maintenance purposes as well as to test recording channels during their development and manufacture.

Abstract: An adjustable near unity power factor is achieved while reducing harmonics in a switch-mode power supply by replacing the conventional diode bridge in the front end with an H-bridge driver. Two feedback loops are required, one feedback loop is used to regulate a DC bulk voltage by comparing the DC bulk voltage to a reference voltage and generating an error signal therefrom. A programmable offset is applied to the error signal for adjusting the power factor. A second feedback loop samples and scales the AC input voltage for use as a scaled replica of the input current. The actual input current is then compared to the scaled replica current to produce a second error signal. The two error signals are multiplied to determine the desired input current wherein the desired input current follows the AC input voltage. The desired input current is pulse width modulated by a fixed frequency sawtooth waveform for providing switching signals for controlling the H-bridge driver.

Abstract: A plurality of parallel processing devices such as compression/decompression units can be tied together to sequentially process equal amounts or sets of data from a stream of data. Hardware in the upper level of each device acts as a demultiplexer to control the acceptance of only its set of data to transfer control to permit the next device to accept data and also stores its set for compaction. Essentially identical hardware in the lower half of each device acts as a multiplexer to control the acceptance of its compacted set of data to store the compacted set and to place the compacted set into the original sequence of the stream of data for storage on the tape media. The lower half reverses its role when the compacted set of data is retrieved from the media to act as a demultiplexer for the decode sequence while the upper half acts as a multiplexer to resequence the decompacted sets into its original stream.

Abstract: Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices.