Abstract: An optical fiber mechanical splice comprises a pair of gripping members and a resilient biasing member. Each gripping member has a gripping surface. One of the gripping surfaces has a v-groove for receiving and aligning optical fiber ends. The v-groove is defined by walls of a plastically deformable material. The resilient biasing means acts between the gripping members to resiliently bias the gripping surfaces of the gripping members toward one another. In use of the mechanical splice, the gripping surfaces are urged toward one another with optical fiber ends in abutting alignment in the v-groove. The walls of the v-groove plastically deform around the fiber ends to provide a larger area of contact between the fiber ends and the walls of the v-groove.

Abstract: An electrically tunable interference filter comprises a semiconductor body which has a plurality of semiconductor layers. Each semiconductor layer comprises first and second sublayers which together define a heterojunction and first and second portions which together define a pn junction located at or closely adjacent to the heterojunction. Electrical contacts are provided for biasing the pn junctions. Application of a forward bias to some of the pn junctions causes injection of carriers from the second sublayers across the heterojunctions into the first sublayers to modify the refractive index of the first sublayers. Application of a reverse bias to other of the pn junctions enhances an inherent electric field at the pn junctions to modify the refractive indices of regions adjacent to the pn junctions. The applied reverse bias also depletes carriers from regions of the first and second sublayers to modify the refractive indices of those regions.

Abstract: In a method for making integrated circuits, a semiconductor substrate is provided which carries a plurality of unconnected devices of a first device type at regularly spaced regions of the substrate and a plurality of unconnected devices of a secound, distinct device type at substantially all regions of the substrate other than those carrying devices of the first device type, and at least one interconnection layer is formed on the substrate to interconnect selected ones of the devices of the first device type and the devices of the second device type to define a plurality of integrated circuits. Pad regions may be formed over unconnected devices for connection of the integrated circuits to package terminals. The integrated circuits are separated by regions containing unconnected devices, and the semiconductor substrate may be scribed and broken or otherwise cut in these regions to separate the integrated circuits.

Abstract: A three terminal semiconductor device relies on resonant tunnelling through a quantum well resonator for its operation. The device has a first layer of a narrow bandgap semiconductor, a second layer of a narrow bandgap semiconductor, and a quantum well resonator between the first layer of a narrow bandgap semiconductor and the second layer of a narrow bandgap semiconductor. The quantum well resonator comprises a first layer of a wide bandgap semiconductor, a second layer of a wide bandgap semiconductor, and a third layer of a narrow bandgap semiconductor between the first layer of a wide bandgap semiconductor and the second layer of a wide bandgap semiconductor. All of the layers referred to above have a common conductivity polarity.

Abstract: An optical fiber splice retainer comprises a base member having a groove extending along a reference surface of the base member, resilient biasing means carried by the base member, and three gripping members which are urged by the resilient biasing means into a gripping position against the reference surface to span the groove at respective gripping locations along the groove. The gripping members are movable against the urging of the resilient biasing means away from the reference surface to permit insertion of optical fibers into the grooves. The gripping members are permitted to close on the inserted optical fibers to clamp the optical fibers in the groove with the fibers in axial alignment. A jig is provided for holding the splice retainer and for urging the gripping members away from the reference surface as required during insertion and alignment of the optical fibers.

Abstract: A Metal-Semiconductor-Metal (MSM) photodetector comprises a semiconductor substrate, a semiconductor barrier layer on the substrate, a thin semiconductor active layer on the barrier layer, and at least two electrical contacts to the active layer. The barrier layer prevents carriers generated deep in the substrate from reaching the contacts. As it is the delayed detection of these carriers which limits the useful operating speed or bandwidth of conventional MSM photodetectors, the MSM photodetector according to the invention is capable of higher speed operation than conventional MSM photodetectors.

Abstract: A monolithically integrated structure comprises a laser diode, a photodetector diode and a reference diode which are monolithically integrated on a common substrate. The photodetector diode is optically coupled to the laser diode. The reference diode is substantially identical to the photodetector diode and optically decoupled from the laser diode. When substantially equal reverse biases are applied to the photodetector diode and the reference diode, the reference diode conducts a leakage current which can be used to substantially cancel the leakage current of the photodetector diode. The monolithically integrated structure may also include a modulator diode which is monolithically integrated on the common substrate and optically coupled to the laser diode. The monolithically integrated structure is useful in optical communications systems.

Abstract: An edge emitting optoelectronic source is integrally formed on a surface of a semiconductor substrate. An optical waveguide is integrally formed on the same surface of the substrate adjacent to the source. The waveguide is aligned with the source for optical coupling of the source to the waveguide. The waveguide comprises an optical diverter for diverting at least a portion of any light propagating along the waveguide toward the source through a surface of the waveguide. An optoelectronic detector is secured to that surface of the waveguide through which light is diverted for receiving light diverted through that surface. The resulting optoelectronic apparatus is suitable for launching and detecting optical signals in large volume bidirectional optical fiber transmission systems.

Abstract: In a method for the formation of an isolating oxide layer on a silicon substrate, an anti-nitridation layer is formed on a silicon substrate at locations where isolating oxide is desired. The anti-nitridation layer has openings therethrough which expose the silicon substrate at locations where isolating oxide is not desired. A thin silicon nitride layer is selectively grown at the locations where isolating oxide is not desired by nitridation of the exposed silicon substrate. Isolating oxide is then selectively grown at the locations where isolating oxide is desired. The thin silicon nitride layer inhibits oxide growth at the locations where isolating oxide is not desired. The method reduces "bird's beak" formation and is particularly applicable to high density IGFET devices.

Abstract: An optical fiber connector element comprises a connector body having a passage extending therethrough, the passage having a forward portion for receiving an optical fiber and a rearward portion which is wider than the forward portion for receiving an optical fiber and surrounding protective material, and an optical fiber stub secured within the forward portion of the passage, the optical fiber stub having a forward end surface which has an optical finish. The connector element is used to terminate an optical fiber cable by cutting the cable to a desired length, stripping back an end portion of protective material surrounding an optical fiber of the cable to expose an end portion of the optical fiber, and securing the exposed fiber end portion and an end portion of the protective material remaining on the fiber in the connector body passage with the fiber end portion in abutment and axial alignment with the fiber stub.

Abstract: In methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer which covers the semiconductor devices at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric insulating layer is formed over the first substantially planar dielectric insulating layer and the seed material, the second layer having openings extending therethrough at the predetermined locations to expose at least a portion of the seed material, and conductive material is selectively deposited on the exposed seed material to fill the openings. The seed material may be a material in the group consisting of aluminum alloys, refractory metals and metal silicides, or may be SiO.sub.2 selectively implanted with silicon ions. The insulating material may be SiO.sub.2.

Abstract: An edge-coupled optoelectronic device is mounted in a TO-style package which comprises a substrate assembly, a circular header and a cylindrical cap. A substrate and an insulating cover of the substrate assembly extend through an opening of the circular header and are secured in that opening. The optoelectronic device is secured to the substrate at a device support location. Electrical conductors are wire-bonded at contacts of the optoelectronic device and at corresponding device contacts of the substrate assembly to electrically connect the contacts of the optoelectronic device to respective conductors of the substrate assembly. The cylindrical cap is secured onto the header over the optoelectronic device.

Abstract: In a method for planarizing an insulating layer, the height of steps in a layer of insulating material are reduced while tapering side walls of the steps by forming a layer of sacrificial material between the steps and etching the insulating material and the sacrificial material in a low pressure plasma comprising reactive ions and facetting ions. This method combines many of the advantages of Resist Etch Back (REB) and argon facetting techniques while reducing the deleterious effects of macroloading and microloading.

Abstract: A fiber optic coupler has a cylindrical rod protruding along the apex of an angled block. An optical waveguide is mounted to extend around part of the circumferential of the rod. A transparent body is located on the side of the fiber remote from the rod, and the rod and the body are biased together to bend the fiber around the rod surface and to form an intimate contact between the transparent body and the curved part of the fiber. A light input or output device is positioned to direct light at or receive light from the curved fiber part through the transparent body.

Abstract: A logic gate comprises a bipolar switching transistor and a depletion mode field effect load device. A current independent voltage source and a voltage independent current source are connected in series between an input terminal of the logic gate and a base of the bipolar transistor. The voltage independent current source is a depletion mode field effect transistor having a source and drain which are connected in series with the current independent voltage source and the base of the bipolar transistor. A feedback device is connected in series between a gate of the current source field effect transistor and a gate of the load transistor. A discharge device is connected in parallel with the current independent voltage source for actively discharging a base-emitter junction of the bipolar transistor during switching of the bipolar transistor from an on state to an off state. The logic gate is particularly suitable for use in memory elements.

Abstract: In methods and apparatus for testing a digital system, system terminals used for coupling input signals into the system and output signals out of the system during normal operation of the system are connected in parallel to a single boundary register. The boundary register is operable to pass input signals and output signals transparently through the boundary register while accumulating together the input signals and the output signals. For testing purposes, the digital system and boundary register are run through a predetermined number of clock cycles while passing known input signals through the boundary register into the system. The known input signals and output signals provided by the digital system are concurrently accumulated within the boundary register to generate a test result pattern.

Abstract: A low power, high noise margin logic gate comprises: an input terminal, an output terminal, and first and second voltage supply terminals; an enhancement mode switching FET having a gate connected to the input terminal, a source and a drain; a load device connected between the drain of the switching FET and the first voltage supply terminal; a feedback device connected between the source of the switching FET and the second voltage supply terminal; a two terminal level shift device connected between the drain of the switching FET and the output terminal; and an enhancement mode pulldown FET having a gate connected to the source of the switching FET, a source connected to the second voltage supply terminal, and a drain connected to the output terminal. The logic gate as defined above operates as an invertor.

Abstract: An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.

Abstract: In a method and apparatus for inhibiting ice mass formation around equipment housed in a chamber subject to water penetration, a plurality of compressible, non-absorbent, smooth-surfaced blocks are packed around the equipment to substantially fill the chamber. The blocks are provided with handles for their placement in and removal from the chamber. The blocks are particularly useful for inhibiting ice mass formation in shallow underground chambers housing telecommunications cable equipment.

Abstract: In a method of filling a contact hole of a semiconductor device, a layer of conducting material, such as a metal silicide, is formed on side walls of the contact hole, and metal is selectively deposited on the bottom of the contact hole and on the layer of metal silicide on the side walls of the contact hole to substantially fill the contact hole. The method provides a contact structure comprising a contact region of the semiconductor device defining the bottom of the contact hole, a layer of conducting material, such as a metal silicide, on the side walls of the contact hole, and a metal plug substantially filling the contact hole. The metal plug adheres to the layer of metal silicide on the side walls of the contact hole and to the contact region defining the bottom of the contact hole.