Abstract: A protective covering constructed from an electrostatically charged sheet having a top and bottom surface and an absorbent layer. The absorbent layer has top and bottom surfaces, the bottom surface of the absorbent layer being bonded to the top surface of the electrostatically charged sheet. The absorbent layer is divided into a plurality of cells for containing liquid spilled on the absorbent layer. The absorbent layer can be constructed from paper, open cell foam, fibrous mat, or any other absorbent material. In the preferred embodiment of the present invention, the cells are constructed by providing hydrophobic barriers in the absorbent layer. The barriers can be constructed from paraffin, plastic, or any other material that can penetrate the absorbent layer. In one embodiment of the present invention, a hydrophobic layer is bonded to the top surface of the absorbent layer.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: A data acquisition circuit for a particle detection system that allows for time tagging of particles detected by the system. The particle detection system screens out background noise and discriminate between hits from scattered and unscattered particles. The detection system can also be adapted to detect a wide variety of particle types. The detection system utilizes a particle detection pixel array, each pixel containing a back-biased PIN diode, and a data acquisition pixel array. Each pixel in the particle detection pixel array is in electrical contact with a pixel in the data acquisition pixel array. In response to a particle hit, the affected PIN diodes generate a current, which is detected by the corresponding data acquisition pixels. This current is integrated to produce a voltage across a capacitor, the voltage being related to the amount of energy deposited in the pixel by the particle. The current is also used to trigger a read of the pixel hit by the particle.

Abstract: An apparatus for decompressing an image that has been compressed by an image compression system in which the image is first repetitively filtered in one direction to produce a series of sub-images which are then repetitively filtered in a second direction to produce an image representation having a plurality of sub-images in which each sub-image has a different spatial frequency content is disclosed. The decompression apparatus reverses the filtering process to recover the original image.

Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.