Patents Represented by Attorney Campbell Nelson Whipps
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Patent number: 8082037Abstract: A form for retaining a battery in implantable medical device includes outer edge and first and second opposing major surfaces. The first major surface of the form includes a recess, a ridge disposed between the recess and the outer edge, and a trough forming element disposed between the ridge and the outer edge. The ridge is configured to engage at least a portion of a major surface of the battery retained in the form. The trough forming element has first and second edge surfaces positioned to engage an edge surface of the retained battery to form a trough configured to receive adhesive. The recess is disposed adjacent the ridge and is configured to allow for expansion of the retained battery during recharge. The retention assembly is configured to secure the first major surface of the battery against the ridge to prevent adhesive from leaking from the trough into the recess.Type: GrantFiled: July 12, 2007Date of Patent: December 20, 2011Assignee: Medtronic, Inc.Inventors: Steve T. Deininger, Charles E. Peters, Jeffrey J. Clayton
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Patent number: 8072014Abstract: A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.Type: GrantFiled: October 13, 2010Date of Patent: December 6, 2011Assignee: Seagate Technology LLCInventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
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Patent number: 8068359Abstract: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.Type: GrantFiled: November 18, 2010Date of Patent: November 29, 2011Assignee: Seagate Technology LLCInventors: Hai Li, Yiran Chen, Hongyue Liu, Xuguang Wang
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Patent number: 8059450Abstract: Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. This step is repeated until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until all the high resistance state resistance value is less than the upper resistance limit value.Type: GrantFiled: October 7, 2010Date of Patent: November 15, 2011Assignee: Seagate Technology LLCInventors: Haiwen Xi, Song S. Xue
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Patent number: 8059453Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.Type: GrantFiled: January 24, 2011Date of Patent: November 15, 2011Assignee: Seagate Technology LLCInventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
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Patent number: 8058646Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.Type: GrantFiled: February 23, 2009Date of Patent: November 15, 2011Assignee: Seagate Technology LLCInventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
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Patent number: 8054677Abstract: A magnetic tunnel junction cell having a free layer and first pinned layer with perpendicular anisotropy, the cell including a coupling layer between the free layer and a second pinned layer, the coupling layer comprising a phase change material switchable from an antiferromagnetic state to a ferromagnetic state. In some embodiments, at least one actuator electrode proximate the coupling layer transfers a strain from the electrode to the coupling layer to switch the coupling layer from the antiferromagnetic state to the ferromagnetic state. Memory devices and methods are also described.Type: GrantFiled: October 9, 2008Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventor: Jianxin Zhu
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Patent number: 8053749Abstract: A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.Type: GrantFiled: February 20, 2009Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventors: Roger Glenn Rolbiecki, Andrew Carter, Yong Lu
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Patent number: 8054675Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.Type: GrantFiled: February 16, 2011Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
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Patent number: 8053255Abstract: Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer.Type: GrantFiled: March 3, 2009Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventors: Kaizhong Gao, Haiwen Xi, Wenzhong Zhu, Olle Heinonen
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Patent number: 8053244Abstract: A biosensor is described. The biosensor includes a fixed multilayer stack providing a magnetization oscillation, a voltage source electrically coupled to the fixed multilayer stack, and a binding molecule covalently bonded to the biosensor. The voltage source provides a direct current through the fixed multilayer stack to generate the magnetization oscillation and a target molecule including a magnetic nanoparticle forms a complex with the binding molecule and alters the magnetization oscillation.Type: GrantFiled: August 13, 2008Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventors: Pat J. Ryan, Haiwen Xi, Insik Jin
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Patent number: 8054673Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.Type: GrantFiled: April 16, 2009Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventors: Xuguang Wang, Yong Lu, Hai Li, Hongyue Liu
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Patent number: 8045370Abstract: A magnetic tunnel junction memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a magnetic tunnel junction memory unit includes applying a first read current through a magnetic tunnel junction data cell to form a first bit line read voltage, then applying a first magnetic field through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell, and then applying a second read current thorough the magnetic field modified magnetic tunnel junction data cell to form a second bit line read voltage. The first read current being less than the second read current. Then comparing the first bit line read voltage with the second bit line read voltage to determine whether the magnetic tunnel junction data cell was in a high resistance state or a low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed.Type: GrantFiled: August 27, 2010Date of Patent: October 25, 2011Assignee: Seagate Technology LLCInventors: Wenzhong Zhu, Yiran Chen, Dimitar V. Dimitrov, Xiaobin Wang
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Patent number: 8043732Abstract: Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization.Type: GrantFiled: November 11, 2008Date of Patent: October 25, 2011Assignee: Seagate Technology LLCInventors: Paul E. Anderson, Song S. Xue
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Patent number: 8045366Abstract: Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit.Type: GrantFiled: March 3, 2009Date of Patent: October 25, 2011Assignee: Seagate Technology LLCInventors: Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Haiwen Xi, Kaizhong Gao, Olle Heinonen, Wenzhong Zhu
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Patent number: 8039913Abstract: A magnetic stack with a multilayer free layer having a switchable magnetization orientation, the free layer comprising a first ferromagnetic portion and a second ferromagnetic portion with an electrically conducting non-magnetic intermediate layer between the first portion and the second portion. The magnetic stack also includes a first ferromagnetic reference layer having a pinned magnetization orientation, a first non-magnetic spacer layer between the free layer and the first reference layer, a second ferromagnetic reference layer having a pinned magnetization orientation, and a second non-magnetic spacer layer between the free layer and the second reference layer.Type: GrantFiled: April 17, 2009Date of Patent: October 18, 2011Assignee: Seagate Technology LLCInventors: Yuankai Zheng, Zheng Gao, Xuebing Feng
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Patent number: 8039394Abstract: A method of forming a layer of alpha-tantalum on a substrate including the steps of depositing a layer of titanium nitride on a substrate; and depositing a layer of alpha-tantalum on the layer of titanium nitride, wherein the deposition of the alpha-tantalum is carried out at temperatures below about 300° C.Type: GrantFiled: June 26, 2009Date of Patent: October 18, 2011Assignee: Seagate Technology LLCInventors: Ivan Petrov Ivanov, Wei Tian, Mallika Kamarajugadda, Paul E. Anderson
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Patent number: 8035177Abstract: A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents.Type: GrantFiled: April 17, 2009Date of Patent: October 11, 2011Assignee: Seagate Technology LLCInventors: Xiaohua Lou, Yuankai Zheng, Wenzhong Zhu, Wei Tian, Zheng Gao
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Patent number: 8026732Abstract: A probe system that has a probe body comprising at least three arms extending from a central region and a probe tip centrally located on the probe body in the central region. A substrate is proximate the probe body opposite the probe tip. A first electrode is positioned to provide a centrally positioned voltage across the probe body and the substrate and a second electrode set is positioned radially outward from the first electrode, to provide an outer voltage across at least one of the at least three arms and the substrate. The probe structure may have, for example, four arms. Methods of actuating the probe tip are provided.Type: GrantFiled: November 17, 2008Date of Patent: September 27, 2011Assignee: Seagate Technology LLCInventors: Dadi Setiadi, Wayne Bonin
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Patent number: 8022547Abstract: A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode.Type: GrantFiled: November 18, 2008Date of Patent: September 20, 2011Assignee: Seagate Technology LLCInventors: Venugopalan Vaithyanathan, Wei Tian, Insik Jin