Abstract: Methods, apparatus, and computer program products provide dynamic replacement communication identification (ID) service. A request is received from a user for dynamic replacement communication ID from a current location of the user. The user requesting dynamic replacement communication ID is authenticated. A user profile of the user requesting dynamic replacement communication ID is retrieved. A current profile of the current location is replaced with the user profile of the user.
Abstract: A system and method for an extendable software interface includes a software architecture for use in a mobile device having a processor and a memory device. The software architecture includes a set of first-order controller software instructions configured to interface the application program with a first-order data model, and a first-order data object stored in the memory device in the form of the first-order data model. The first-order data object includes a second-order data object. A second-order set of controller software instructions configured to interact with the second-order data object is also included in the software architecture.
Abstract: Disclosed herein are novel electrochromic materials. The electrochromic materials produce various colors and have bistability to achieve red-green-blue full colors. Therefore, the electrochromic materials can be used in a variety of electrochromic devices. Also disclosed herein are electrochromic devices fabricated using the electrochromic materials.
Abstract: Provided is a method of preparing a patterned spot microarray using a photocatalyst. The method comprises coating the photocatalyst on a substrate to form a photocatalyst layer, coating a composition comprising a functional group to be connected to a biomolecule on the photocatalyst layer to form an organic layer, spotting the biomolecule on the organic layer, positioning a photomask above a spot of the biomolecule; and irradiating the spot through the photomask to pattern the spot.
Abstract: Methods and apparatus for evaluating a formation include conveying a formation evaluation tool in a borehole on a tubular carrier extending from a surface location at least to the formation evaluation tool. A cable is conveyed to the formation evaluation tool and communication between the formation evaluation tool and the cable is established after the formation evaluation tool is moved to a selected borehole location.
Abstract: The invention relates to a method for joining a first acoustic panel (2), having a cellular structure of the honeycomb type, with a second acoustic panel (2), wherein said method comprises the steps of: inserting at least one mandrel, (5, 8) having a shape adapted to the cells (3), into at least one cell (3) located in the vicinity of a junction edge (6) of the acoustic panel; passing a roller (12) on said junction edge of the acoustic panel; joining the junction edge of the acoustic panel together with a junction edge (6?) of the second panel and connecting the same by applying a linking means.
Abstract: A method for determining data packet transmission times in an Ethernet protocol including, receiving a first data packet having a first data packet send time, wherein the first data packet send time is a time the data packet is sent by a source transmitter, subtracting the first data packet send time from a first data packet receive time to yield a first data packet transmission time, wherein the first data packet receive time is the time the data packet is received by a destination receiver, comparing the first data packet transmission time to a third time, determining whether a difference between the first data packet transmission time and the third time exceeds a threshold value, and sending a notification of a transmission delay responsive to determining that the difference between the first data packet transmission time and the third time exceeds the threshold value.
Type:
Grant
Filed:
March 18, 2008
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Abstract: A system and method for an extendable software interface includes software architecture for use in a mobile device having a processor and a memory device. The software architecture includes a set of first-order controller software instructions configured to interface the application program with a first-order data model, and a first-order data object stored in the memory device in the form of the first-order data model. The first-order data object includes a second-order data object. A second-order set of controller software instructions configured to interact with the second-order data object is also included in the software architecture.
Abstract: The present invention is for a catalyst, a process for making the catalyst and a process for using the catalyst in aromatization of alkanes having three to five carbon atoms per molecule, such as propane, to aromatics, such as benzene, toluene and xylene. The catalyst is an aluminum-silicon zeolite having a silicon to aluminum atomic ratio (Si:Al) greater than 15:1, such as MFI or ZSM-5, on which germanium, aluminum and a noble metal, such as platinum, have been deposited. The catalyst may be bound with magnesia, alumina, titania, zirconia, thoria, silica, boria or mixtures thereof. The aluminum and germanium may be deposited simultaneously on the zeolite.
Type:
Grant
Filed:
January 12, 2012
Date of Patent:
September 25, 2012
Assignee:
Saudi Basic Industries Corporation
Inventors:
Scott Stevenson, Gopalakrishnan G. Juttu, Michael Mier, Robin J. Bates, Dustin Farmer, Scott Mitchell, Alla K. Khanmamedova
Abstract: A method that provides for dynamic loop transfer for a method having a first set of instructions being executed by an interpreter is provided. An execution stack includes slots for storing a value of each local variable known to each subroutine while the subroutine is active.
Type:
Grant
Filed:
August 30, 2007
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.
Type:
Grant
Filed:
November 2, 2009
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Inventors:
Kai D. Feng, Thomas J. Fleischman, Ping-Chuan Wang, Xiaojin Wei, Zhijian Yang
Abstract: A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage.
Abstract: A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.
Type:
Grant
Filed:
February 22, 2012
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Inventors:
Zhihong Chen, Dechao Guo, Shu-jen Han, Kai Zhao
Abstract: An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.
Type:
Grant
Filed:
November 13, 2009
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Inventors:
Bruce G. Elmegreen, Ralph Linsker, Dennis M. Newns, Bipin Rajendran, Roger D. Traub
Abstract: A display device includes a pixel electrode disposed on a first substrate, and including a first portion, a second portion and a connection portion disposed between the first portion and the second portion, a capacitor line disposed on the first substrate and between the first substrate and the connection portion, a nonsymmetrical shaped capacitor electrode disposed on the first substrate and overlapping the pixel electrode and the capacitor line, and electrically connected to the pixel electrode through contact holes, and a common electrode disposed on a second substrate and including first and second opening patterns disposed overlapping the first portion and the second portion of the pixel electrode, respectively.
Abstract: A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is running. In response to issuing the instruction, a state descriptor belonging to the target logical processor is queried to determine whether the target logical processor is currently running. A result is then returned to the first logical processor, the result indicating whether or not the target logical processor is currently running.
Type:
Grant
Filed:
September 6, 2006
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Inventors:
Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski
Abstract: A gas turbine engine is provided and includes a combustor having a first interior in which a first fuel is combustible, a turbine into which products of at least the combustion of the first fuel are receivable, a transition zone, including a second interior in which a second fuel and the products of the combustion of the first fuel are combustible, a plurality of fuel injectors which are configured to supply the second fuel to the second interior in any one of a single axial stage, multiple axial stages, a single axial circumferential stage and multiple axial circumferential stages, a compressor, by which air is supplied to the first and second interiors for the combustion therein, and a control system configured to control relative amounts of the air to the first and second interiors and relative amounts of the first and second fuels supplied to the first and second interiors.
Type:
Grant
Filed:
January 6, 2012
Date of Patent:
September 25, 2012
Assignee:
General Electric Company
Inventors:
Lewis Berkley Davis, Jr., Krishna Kumar Venkataraman, Willy Steve Ziminsky, Geoffrey David Myers
Abstract: Methods, systems, and computer program products for database table aggregation are provided. A method includes encoding first and second components via a waveform definition, the first and second components specifying first and second criteria, respectively, for aggregating data. The method includes generating a complex periodic aggregation waveform (CPAW) having variable-sized square waves representing the components in a repeating pattern corresponding to the definition and the criteria, and which spans a first axis. The method includes providing a maximum byte count for aggregated data stored in a table defined by the first and/or second criteria, aggregating the data in accordance with the criteria, and creating a new table for overflow of data determined for the table when the maximum byte count is exceeded. The method includes updating the CPAW with results of the aggregation and generating a waveform representing the new table along a second axis.
Type:
Grant
Filed:
December 18, 2008
Date of Patent:
September 25, 2012
Assignee:
AT&T Intellectual Property I, L.P.
Inventors:
Arthur Zaifman, Saiprakash Rao, Philip E. Brown
Abstract: A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine.
Type:
Grant
Filed:
January 28, 2008
Date of Patent:
September 25, 2012
Assignee:
International Business Machines Corporation
Inventors:
Matthias Schunter, Axel Tanner, Bernhard Jansen