Abstract: A method, apparatus, and system for generating an image from subsampled, three-component image data. First and second components of the image data are processed to generate a dither index to a dither lookup table. The third component of the image data is dithered. CLUT index data is then generated using the dither data from the dither lookup table and the dithered third-component data. The CLUT index data may then be used to generate the image. In a preferred embodiment, a 14-bit dither index to a 16K dither lookup table is generated from the U and V components of a (4.times.4) block of YUV9 data. The Y components are dithered and then processed with the appropriate dither lookup table data to generate 16 CLUT index values for the (4.times.4) block. The dithering and processing is preferably performed on a row-by-row basis in a pseudo-SIMD fashion.

Abstract: A method and system for generating compressed image signal. The system generates an analog image signal corresponding to the image, generates unencoded three-component image data from the analog image signal, and encodes the unencoded image data. After encoding, the image data has an OPERATING SYSTEM header, a BITSTREAM header, a Y-COMPONENT DATA field, a U-COMPONENT DATA field, and a V-COMPONENT DATA field. Each of the DATA fields has a four-byte MC VECTOR COUNT field, an MC VECTORS field, and an ENCODED DATA field that has interleaved binary tree codes and region codes. The system also stores the OPERATING SYSTEM header, BITSTREAM header, Y-COMPONENT DATA field, U-COMPONENT DATA field, and V-COMPONENT DATA field. In a preferred embodiment, the invention generates compressed video signals.

Abstract: The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

Abstract: There is disclosed herein a stress relieved intermediate insulating layer consisting of one or more layers of spun-on glass lying over a metalization pattern. The spun-on layers are allowed to crack from thermal stress imposed upon the structure. The cracks in the spun-on layers are then filled with a glass layer deposited by CVD or LPCVD.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read-only memories and programmable logic arrays, and allows fabrication of Schottky diodes more compactly than previous structures.

Abstract: An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV.sub.

Abstract: A static RAM cell (11) is constructed utilizing low resistivity positive and negative power supply leads (13,14), thus eliminating the problem of instability of the data stored within the cell. The negative power supply lead is formed of a first layer of low resistivity polycrystalline silicon/tantalum silicide, and the positive power supply lead is formed of a second layer of polycrystalline silicon. The use of a low resistivity negative power supply lead causes the voltage drop on the negative power supply lead to be substantially reduced as compared with prior art devices, thereby providing during the read operation substantially equal voltages to the gates of the two bistable transistors of each cell, thus eliminating the problem of instability during reading.Depletion load devices (11,12) are formed utilizing the layer of polycrystalline silicon as the source, drain and channel and the layer of polycrystalline silicon/tantalum silicide as the gate.

Abstract: An argon-fluorine (ArF) excimer laser is used to selectively heat various Si.sub.3 N.sub.4 materials used in the manufacture of semiconductor devices to elevated temperatures while maintaining active device regions and electrical interconnects at relatively low temperatures, to, for example, anneal the structural layer, induce compositional changes or densification and/or flow of the silicon nitride-based material to round off sharp edges and stops, all without damaging or appreciably affecting the active regions and electrical interconnects of a semiconductor device.

Abstract: A tunable CO.sub.2 gas laser is used to selectively heat various SiO.sub.2 -based materials to elevated temperatures while maintaining an active device region at relatively low temperatures, to, for example, induce densification and/or flow of the SiO.sub.2 -based material to round off sharp edges and stops.

Abstract: A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A.degree., of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950.degree. C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.

Abstract: A novel zero insertion (and removal) force multi-pin coaxial connector for providing connections via controlled impedance paths is formed using a conductive elastomer as a frame (8) which forms the shield of a plurality of coaxial connectors and a plurality of circular openings formed in the conductive elastomer frame, each said opening corresponding to a single coaxial connection. An annular insulating ring (5), which forms the dielectric of an associated one of the coaxial connectors, is located in each annular opening of the conductive elastomer frame and an elastomer through-conductive member (6) which forms the center conductor of its associated coaxial connector is located within the circular opening of each insulating ring. In this manner, the conductive elastomer frame forms the shield of a plurality of coaxial connectors.

Abstract: A method for fabricating a semiconductor structure which reduces substrate current injection from lateral bipolar transistors. A buried layer of a first conductivity type is formed in a semiconductor substrate of opposite conductivity. An epitaxial layer of the first conductivity type is formed such that at least a portion of the epitaxial layer overlies the buried layer. Isolation oxide regions are formed in a epitaxial layer. The isolation oxide regions extend to the substrate to define an island of electrically isolated epitaxial material. A selected impurity of the first conductivity type is introduced into that portion of the epitaxial layer beneath the to-be-formed lateral transistor. The lateral transistor is formed in the epitaxial layer.

Abstract: A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.

Abstract: This invention provides a single integrated circuit device which replaces the non-integrated "encapsulated circuit" of the standard prior art telephone set. The circuit of this invention achieves proper D.C. regulation of the telephone line, by presenting one of several possible D.C. impedances to the telephone line when the telephone set is in the off-hook condition. The circuit of this device provides such regulation by varying the gain relationship of the telephone set for various distances from the central switching office, thereby maintaining a rather uniform signal amplitude in a plurality of telephone sets located at various distances from the central switching office. In one embodiment, this is done using a novel regulator substantially completely formed as part of a single integrated circuit chip containing a receiver amplifier, transmitting amplifier, dialing circuitry and ringing circuitry.

Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.

Abstract: A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

Abstract: A method of programming a cell in a PROM, wherein the cell comprises a bipolar transistor having a floating base, comprises applying a current rising with time across the emitter to collector contacts of the bipolar transistor with the collector contact serving as the reference potential, measuring the time at which the rise in voltage suddenly stops and the voltage drops a small amount, and then holding the current for a selected time following the voltage drop, thereby to insure that the emitter base junction of the bipolar transistor is destroyed while at the same time not damaging the base collector junction of the biplolar transistor.

Abstract: A circuit for providing an identification signal indicative of whether or not an integrated circuit has been repaired includes a circuit which operates at potentials outside the normal range of the integrated circuit. The circuit includes at least one transistor T1 serially connected between a TTL pin 10 of the integrated circuit and a fuse F1. The fuse F1 is also connected to a potential source V.sub.CC. If the integrated circuit is repaired the fuse F1 is opened, and consequently, application of a potential outside the normal range will cause current to flow if fuse F1 has not been opened, and cause no current to flow if fuse F1 has been opened.