Abstract: A static inverter is disclosed for d.c. to a.c. conversion comprising a pair of switching semiconductor devices and a power transformer having primary, secondary and control windings associated with a double apertured linear magnetic core. Each aperture partitions the core cross section in a localized region into two branches. The primary and secondary power windings encircle the full core, which has a closed magnetic path, while the control windings are associated with only a branch. Means are provided to cause one branch to saturate before the other branch and before full core saturation. Saturation of one branch is used to reduce the regenerative feedback and increase the degenerative feedback to provide an advance turn off, allowing charge stored in the switching device to dissipate prior to the end of each conduction period. This mode of the feedback control avoids full core saturation and avoids overstressing the switching devices that full core saturation would produce.

Abstract: The present invention relates to a digitally controlled phase shift network for an analog flux-sensing ferrite phase shifter driver, as would be applied in controlling the phase of individual antenna elements in phased array radar systems. The phase shift network described utilizes analog phase shifters while accepting a digital control input, and provides phase control without need for digital-to-analog converters between the analog phase shifters and their digital inputs. This is accomplished by integrating the volt-time product on the phase shifter secondary windings until the integral reaches a value corresponding to a phase shift increment of predetermined magnitude, dumping the integrator voltage between integrations, counting the number of integrate-and-dump operations to thus yield a digital measure of the phase shift achieved, and comparing such digital count against the digital control input.

Abstract: An infrared imager having (1) sensing sites comprised of three MIS capacitors, one being an optically sensitive receiver capacitor, a second being an optically insensitive transfer capacitor, and a third being an optically insensitive storage capacitor; and (2) storage control circuit for cycling said sensing sites through a plurality of storage cycles, each cycle comprised of transferring a signal charge from said receiver capacitor to the storage capacitor, prior to readout of the stored signal charge, which is substantially free of background charge, from said optically insensitive storage capacitor using either charge-injection device (CID) or charge-coupled device (CCD) techniques.

Abstract: The invention relates to a recursive numerical processor for data in word serial form in which bias errors are reduced by use of a property of two's complement notation. The input data is introduced in two's complement notation. The processor includes a sub-processor, typically a multiplier, introducing a bias error on the order of the least significant bit. The bias error arises from truncation or rounding necessary to avoid word growth in the processor. In accordance with the invention, the sub-processor is provided with a sign inverter at its input and at its output and the two sign inverters perform a double sign inversion on alternate words. Alternate word sign switching causes the error to alternate between being too large and too small (in magnitude), a property of two's complement notation, thus cancelling a very substantial part of the bias error. The invention has application to a number of recursive numerical processors including recursive digital filters.

Abstract: An intermediate frequency sidelobe canceller of the kind including a cancellation loop, with provision added for programming the correlation signal weights which control operation of the loop. This capability is provided by switch means interposed in the cancellation loop within the correlation signal branch thereof and selectively operable to break the loop and then either to substitute for the normally weighted correlation signal to the canceller another signal of different weighting, such as an externally supplied signal, or to retain or "hold" the current value of the correlation signal. Such substitution affords improved canceller operation and adaptability to otherwise difficult operating conditions such as strong clutter and transmitted pulse interference.

Abstract: The electroacoustic transducer disclosed is of double mass loaded piezoelectrically driven type particularly adapted to high power sonar array application. For reducing transducer sensitivity to interference and noise of frequencies at and below the transducer moving assembly mounting resonance, without significant impairment of transducer efficiency even at high power levels in the active mode operating frequency bands, the transducer moving assembly mounting resonance is damped by provision of a resistive coupling which in its preferred form comprises a lossy rubber ring compressed between the transducer housing and the inertia mass. Corona suppression means effective at high power levels of operation as described also are disclosed.

Abstract: Disclosed is a radar signal processor providing Moving Target Indicator (MTI) operation with Constant False Alarm Ratio (CFAR) capability. The processor affords substantially reduced incidence of false alarms due to large clutter scatterer returns which exceed normal detection thresholds even after suppression by conventional MTI processing, and at the same time it affords largely unimpaired subclutter visibility. These capabilities are achieved by paralleling the MTI channel with a second processor channel which provides CFAR operation by imposing an additional detection threshold effective to blank the response of the MTI channel to very large clutter scatterers.

Abstract: The present invention relates to a transducer array having a resolution suitable for imaging objects disposed in a liquid medium and illuminated with sonic energy of short wavelength. The array consists of a plurality of piezoelectric transducers sensing the sonic waves at their extremities and designed to produce corresponding electrical voltages suitable for image formation. While the individual transducers are fabricated from a common monolithic block, a geometry is used which reduces the coupling between the individual transducers. The individual transducers, which vibrate in a longitudinal mode with antinodes at either extremity and nodal regions at the center, are supported at their nodes by a thin web. The thin web then is the means for attaching the array to the frame of the apparatus. Central nodal support of the transducers minimizes stresses on the web from transducer vibration, reduces crosstalk, and improves the resolution of the array.

Abstract: The present invention relates to signed multiplication logic for multiplying two serial binary numbers to obtain a serial binary product, the multiplicand containing magnitude and sign information in two's complement notation, the multiplier containing magnitude information, and the product containing magnitude and sign information in two's complement notation, all three bit streams occurring serially at equal word rates with the least significant bit first in time. The logic is composed of a plurality of largely identical multiplication cells which form partial products which are summed in largely identical summation cells to form the final product. Each multiplication cell stores a multiplier bit, contains a stage of a multiplicand shift register and a stage of a timing waveform shift register. Means are provided for truncation of the multiplicand and product rounding under timing waveform control. The logic is flexible and may be used to form single or double precision products.

Abstract: An automatic gain control system applicable to a television receiver is described. Synchronizing pulses contained in the video detector output are sensed to obtain a measure of the signal strength. This is done by applying the detected output, containing the pulses, to a threshold circuit to produce current increments representative of the excess of said pulses over the threshold. The current increments thus obtained are then applied to a non-linear amplifier which, as a bi-directional source of current, supplies charging or discharging current, depending upon signal strength variation, to an integrating network to obtain a smoothed gain control voltage. The circuit is characterized by both fast attack and fast release and may be used with or without external gating. It is suitable for general AGC control in a television receiver which must be substantially immune to aircraft flutter.