Abstract: A method and an apparatus for protecting fiber-optic cable bundle closures includes a quick disconnect that allows for cabling to the closure to be separated upon the presence of a sudden jerk or pulling force. Additionally, a plurality of quick disconnects are used to effective create modular components out of a fiber-optic cable bundle that, heretofore, has be permanently attached to each other. The quick disconnects are rendered water resistant with the use of rubber boots that cover the quick disconnects to keep moisture out.

Abstract: The present invention incorporates information representing the location and movement of a mobile station in a wireless telecommunications network to manage and control hand-offs, reduce the risk of falsing, prioritize channel assignments and control the power level of channels.

Abstract: Precharge circuitry for reading a data bit from a memory having at least two local bit lines comprises at least two precharge transistors for precharging the at least two local bit lines, at least two “keeper” transistors for keeping the at least two local bit lines, and a NAND gate for receiving the data bit from the memory via one of the at least two local bit lines and switching the at least two “keeper” transistors. The precharge circuitry does not need an additional inverter for switching any of the “keeper” transistors, thereby eliminating additional capacitance associated with the inverter and reducing unnecessary power consumption associated with the “keeper” transistors. Preferably, the transistors used in the precharge circuitry are p-channel metal-oxide-semiconductor field effect transistors (MOSFETs).

Abstract: A circuit generating memory clock with phase advance and delay capability is provided. The phase of the memory clock is controlled by adjusting the configuration register bits. The circuit allows for a high degree of control and flexibility in the memory clock generation in that the memory clock relationship with respect to the memory command and data can be adjusted independently, thereby creating the ability to effectively adjust the memory interface timings such as setup time, hold time, and memory read data access time. Specifically, 0, 90, and 180 degree phase advance ability is combined with the ability to add delay in fine increments to achieve a more granular degree of phase adjustment.

Abstract: Disclosed is a method and apparatus for causing CPUs comprising portions of a fault tolerant process group to operate in an active-standby mode when synchronizing newly on-line CPUs and reverting to an active-replication mode when synchronization is complete. The above is accomplished in one embodiment of the invention by continuing to operate the primary processor in the active-standby mode and updating the newly online CPUs in accordance with a single pass intelligent update algorithm. When synchronization is complete, a message is transmitted to all CPUs in the group causing a reversion to an active-replication mode for all CPUs whether primary or standby. Any already synchronized CPUs that were in a standby mode, when the group is switched to an active-standby mode, are only updated by check-point message data as data synchronization updating record messages being supplied to a newly online CPU are ignored by these already synchronized standby CPUs.

Abstract: Disclosed is an method and apparatus for configuring an H.323 compliant data packet network with a registering function whereby home based users are identified separate from visiting users having other networks as home bases. Thus user location data may be retrieved and/or modified as those users roam to other H.323 compliant networks and register with a gatekeeper at that visited network. The registration of a visiting user with a visited gatekeeper includes the process of assigning a transient identity to the roaming user, obtaining confirmation from the home gatekeeper that roaming is authorized and registering the roaming users present address and transient identity at the home site so that calls received at the home network can be directed to the user at the visited site.

Abstract: A method for providing a first JVM with support for fault tolerance by using information maintained by the first JVM to checkpoint objects that are created, modified, and/or deleted during the process of responding to an event of a transaction. The checkpointed objects are sent to and stored in a second JVM such that the second JVM is fully capable of continuing the processing of the transaction in the event of the failure of the first JVM.