Abstract: A transmitter architecture includes an equalizer and a D/A converter, for high-speed transmission of data across a channel. The equalizer includes a two-tap MAC as part of an N-stage, two-way interleaved FIR filter. The two-tap MAC provides substantial power and area savings over conventional MAC-based FIR filter designs, and may be implemented in short or long communications channels. The D/A converter is decoupled from the equalizer. Its N-bit, binary-weighted driver includes matched unit current generation cells, all of which are fully utilized during each digital-to-analog conversion. The D/A converter remains unchanged, even when the characteristics of the equalizer are changed.

Abstract: An automatic gain control (AGC) system and method for implementing a wide dynamic range automatic gain control (AGC) are disclosed. The AGC system features a large gain adjustment suitable for integration in silicon tuners. The AGC structure employs a pair of classical current steering stages, architecturally arranged to share the gain back-off characteristic in a novel “ping-pong” arrangement. The AGC system and method deliver a wide dynamic range at low power dissipation in radio frequency (RF) systems, but may be implemented as well in other applications.

Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

Abstract: A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.

Abstract: An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cell experience less degradation than in inverter-based memory cells. Guard-banding to account for transistor degradation may be mitigated, or the operating frequency of the memory cell may be increased.

Abstract: A recursive carry-select substitution operation is used to optimize the design of an incrementer and similar logic devices. A carry look-ahead incrementer features XOR gates in which the XOR gates in one or more MSBs of the incrementer can be pushed back by substituting an equivalent carry-select circuit, the carry-select circuit including a multiplexer. The push back operations occur until both inputs of the XOR gates are fed by inverters, allowing an entire stage of inverters to be eliminated in the circuit. Where a bit path includes a buffer comprising two inverters, the inverter size is selected so as to execute as a single stage. The result is a carry look-ahead incrementer in which a stage is eliminated.

Abstract: A display system and method are disclosed. One embodiment of a display system comprises a position arm coupled to a first monitor and a second monitor that are each communicatively coupled to a computer. The system also comprises a position sensor operatively associated with the position arm and the sensor can generate relative position data of the first monitor after a user positions the first monitor adjacent to the second monitor. The system also comprises display logic communicatively coupled to the position sensor and operatively associative with the operating system of the computer, and the display logic can automatically cause display configuration features of the computer to be changed in response to receiving the relative position data.

Abstract: A variety of performance control mechanisms are disclosed, allowing a user of a processor-based system to adjust performance criteria such as processing speed and fan speed. A performance control apparatus includes one or more user-accessible knobs and a display. The knob(s) enable the user to select from a variety of processor and fan speed settings. Other performance-related criteria may also be controlled using the knobs. The display communicates the effect of a change in performance criteria in a manner useful to the user. A performance control application program enables the user to independently pre-select performance criteria for each application program or group of application programs. A performance control icon provides the ability to select performance criteria from within an application program.

Abstract: An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.

Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

Abstract: A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.

Abstract: A method for performing CRC calculations on packets with dynamic headers is disclosed. The header may be changed during transmission across a network. When the header is changed, a CRC associated with the header is recalculated such that a residue of the initial seed value is always obtained. A final CRC covers the entire packet including the header and its header CRC, or just the data portion of the packet. The final CRC remains valid and unchanged during transmission of the packet, allowing an endpoint along the network to confirm the validity of the entire packet. By only changing the CRC associated with the changed portion of the packet (the header CRC), the introduction of errors during transmission of the packet is minimized.

Abstract: A system and method are disclosed in which flex cables are affixed to PCBs, for providing high-speed signaling paths between ICs disposed upon the PCBs. The flex cables are fixably attached to the PCBs so as to substantially mimic their structural orientation. Where the configuration includes more than one PCB, the flex cables include multiple portions which are temporarily separable from one another and from the die, using flex-to-flex and flex-to-package connectors, allowing field maintenance of the configuration. By routing the high-speed signals between ICs onto the flex cable, single-layer PCBs can be used for non-critical and power delivery signals, at substantial cost savings. By disposing the flex cables onto the PCB rather than allowing the cables to float freely, the configuration is thermally managed as if the signals were on the PCB and cable routing problems are avoided.

Abstract: A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

Abstract: A system and method for automatically adjusting microprocessor activity following thermal stress of a voltage regulator is disclosed. A thermal monitoring circuit determines whether the voltage regulator has exceeded a predetermined temperature. The thermal monitoring circuit may employ a temperature-sensing component such as a thermistor to determine the temperature or may derive the temperature indirectly, based on the average input (or output) current. When the over-temperature condition occurs, a signal activates the PROCHOT#, or similar, pin on a microprocessor, throttling the microprocessor clock. Where the microprocessor includes no internal power-reducing feature, the signal throttles an external clock coupled to the microprocessor. In either case, execution of the microprocessor is slowed down. At all times, the voltage regulator maintains the ability to supply continuous current to the microprocessor.

Abstract: A system for conducting transistor performance analysis is disclosed, in which automatic graph plotting is interactively enhanced with human judgment. The system includes executing transistor performance analysis software, which receives templates specifying parameters, graph charting options, and algorithms, as well as a database of transistor values, as its inputs. The software produces an output document with linked graphs and a summary report. The software extracts, filters and applies statistical regression to large quantities of data. The software also applies statistical filtering to the data and automatically plots hundreds of charts and graphs based on the data. Graphs are color-coded to highlight relationships that suffer from unusually high noise in the data. Users can manually adjust lines on the graphs, which are automatically reflected in dependent graphs and the summary report. Changes to program methodology can be achieved by changing the template rather than by modifying the software.

Abstract: An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (Dk), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the Dk, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.

Abstract: A system for mounting heatsinks, in particular, high-mass heatsinks, on printed circuit boards, such as motherboards. The mounting system includes a backplate, disposed beneath the motherboard, with pins protruding up through the motherboard, and a linkage assembly, which is fixably attached to a base portion of a heatsink assembly. The linkage assembly includes scoops, for grasping the pins during engagement, and a ratcheting system, for compressing the heatsink and thermal interface material onto the package. The mounting system is designed to effectively distribute the heatsink weight, as well as the forces caused by chronic and dynamic stresses, through, rather than upon the motherboard, such as to a chassis. The mounting system thus alleviates stress cracks, component pullout, solderball stress, and other damaging conditions to the motherboard. The mounting system may be engaged and disengaged without the use of tools.

Abstract: An optical system including two or more micromirror arrays is disclosed. The micromirror arrays include alternately disposed transparent and opaque surfaces. The system spatially separates an image toward the micromirror arrays, the image is reflected from the micromirrors, and the reflected image is combined into a composite image that can be displayed or projected. Control and support circuitry that is typically disposed beneath the transparent surfaces of the micromirror arrays can be disposed beneath the opaque surfaces.

Abstract: An LCOS display, including specially manufactured spacers, and a process for making the display, are disclosed. The spacers ensure a uniform cell gap along the entire display. The spacers occupy a region between pixels, such that they do not interfere with light modulation and are not visible during magnification. The spacers are manufactured using known deposition, lithography and etching techniques, and are made from widely available materials. The process results in a high yield of high-quality LCOS displays.