Abstract: A system, method, and service associated with a computing grid or a virtual organization include a request for proposal (RFP) generator, where the RFP describes a data processing task. The RFP is provided to multiple resource providers via the computing grid where each of the resource providers is potentially suitable for performing the data processing task on behalf of the resource consumer. An RFP response processor receives and evaluates RFP responses generated by one or more of the resource providers. An exception processor accessible to the RFP response processor evaluates any exception in the RFP to determine if the exception disqualifies the RFP response. The exceptions may include, for example, job time limit exceptions, resource requirement exceptions, hardware/software platform requirement exceptions and others. Exception rules may be defined to guide the evaluation of the exception.

Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).

Abstract: A method and software for fulfilling a resource request in a data processing network includes specifying characteristics of the requested resource responsive to detecting the resource request. A set of attributes is then derived from the specified characteristics. The specified characteristics indicate broad or general properties of the needed resource while the derived attributes preferably indicate the hardware and software components of a resource ideally suited to fulfill the resource request. Attribute information associated an available resource is then evaluated against the attributes derived from the specified characteristics. An available resource is then selected, based on the evaluation, to satisfy the resource request. The attributes of the selected resource best match the attributes derived from the specified characteristics.

Abstract: A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of an XOR gate are sourced by the representative gate and a candidate gate. A speculatively reduced netlist is generated by replacing the representative gate as the source gate for edges sourced by a candidate gate in the original design. The speculatively reduced netlist is then used either to verify formally the equivalence of the gates by applying a plurality of transformation engines to the speculatively reduced netlist or to perform incomplete search and, if none of the equivalence gates is asserted during the incomplete search, any verification results derived from the incomplete search can be applied to the original model.

Abstract: Event vectors are included in an instruction tracking structure of a processor to collect history for every instruction flowing through the processor. Such an event vector, by its nature, cannot be whole until the vector's corresponding instruction completes. However, some information for the event vector is collected earlier, i.e., as the instruction flows through the processor prior to completion. Upon completion of the instruction, the instruction's event vector is examined. In each case a determination is made from the instruction history contained in the event vector as to whether a particular instruction has or has not caused or encountered an event of interest. Responsive to the determination, and possibly other information, a selection is made between saving event vector information and discarding the information.

Abstract: Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when the corresponding byte in the cache is written. The mask bits are used in a reordered operating sequence to selectively write data from system memory into the cache after a write into cache. Data transfer performance is improved significantly in that the selective writing of data from system memory to cache can be completely eliminated when the mask bits indicate that a whole unit of the cache, typically a cache line, has been written during the data transfer into the cache.