Patents Represented by Attorney, Agent or Law Firm Casey P. August, Esq.
  • Patent number: 6816790
    Abstract: Techniques for analyzing gene expression levels are provided. In one aspect of the invention, the technique provides a method for determining a concentration level of a target nucleic acid, the target nucleic acid comprising at least one target oligonucleotide. The method determines (i) a measure of affinity value of the target oligonucleotide with a probe oligonucleotide; and (ii) a hybridization intensity value for the target oligonucleotide and the probe oligonucleotide at a probe spot. The measure of affinity value and the hybridization intensity value are used to determine the concentration level of the target nucleic acid.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey Grinstein, Glenn Allen Held, Yuhai Tu
  • Patent number: 6785650
    Abstract: Generally, the present invention provides the ability to present a mixed display of a transcription to a user. The mixed display is preferably organized in a hierarchical fashion. Words, syllables and phones can be placed on the same display by the present invention, and the present invention can select the appropriate symbol transcription based on the parts of speech that meet minimum confidences. Words are displayed if they meet a minimum confidence or else syllables, which make up the word, are displayed. Additionally, if a syllable does not meet a predetermined confidence, then phones, which make up the syllable, may be displayed. A transcription, in one aspect of the present invention, may also be described as a hierarchical transcription, because a unique confidence is derived that accounts for mixed word/syllable/phone data.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Sara H. Basson, Dimitri Kanevsky, Benoit Emmanuel Maison
  • Patent number: 6785672
    Abstract: In a sequence homology detection aspect of the invention, a computer-based method of detecting homologies between a plurality of sequences in a database and a query sequence comprises the following steps. First, the method includes accessing patterns associated with the database, each pattern representing at least a portion of one or more sequences in the database. Next, the query sequence is compared to the patterns to detect whether one or more portions of the query sequence are homologous to portions of the sequences of the database represented by the patterns. Then, a score is generated for each sequence detected to be homologous to the query sequence, wherein the sequence score is based on individual scores generated in accordance with each homologous portion of the sequence detected, and the sequence score represents a degree of homology between the query sequence and the detected sequence.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Aris Floratos, Isidore Rigoutsos
  • Patent number: 6743670
    Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J Radens, Joseph F. Shepard, Jr.
  • Patent number: 6721807
    Abstract: An improved method and system is described for implementing double dispatch extensibly and efficiently in single-dispatch object-oriented programming languages. Objects of type Visitor encapsulate double dispatch functionality, while objects of type Element act as operands. Double dispatch takes place by calling Accept on an object of type Element, passing an object of type Visitor as an argument. Concrete classes of type Element are added in groups, each group deriving from an abstract subclass of Element. An AbstractElement class augments the Element interface with an Accept operation that takes an object of type AppVisitor as an argument, where AppVisitor is an abstract subclass of Visitor. AppVisitor overrides the base class Visit operation to test the type of its Element argument, casting it into an AppElement and calling its augmented Accept.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventor: John Matthew Vlissides
  • Patent number: 6672775
    Abstract: A method and system is disclosed for downloading data, such as a web page, over a network such as the internet. The method includes the steps of (a) initiating a web page download request with a requesting entity having a first network address, the requesting entity being connected to the network; (b) fulfilling the web page download request with a web page source entity having a second network address; (c) transmitting a requested web page to a destination entity having a third network address; and (d) receiving and storing the requested web page in the destination entity for subsequent use by a user of the requesting entity. In this manner a low performance data processor may specify certain web pages to be downloaded to a higher performance processor over a higher bandwidth link, and may also specify postprocessing to be performed on retrieved web pages prior to a user of the first data processor accessing the stored web pages.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: January 6, 2004
    Assignee: International Business Machines Corporation
    Inventor: Chandrasekhar Narayanaswami
  • Patent number: 6671626
    Abstract: Generally, the present invention provides and uses a set of descriptors of three-dimensional molecular property fields. A portion of the descriptors are calculated in such a way as to separate property fields from the underlying structure of the molecule. These descriptors are calculated through reference to a property field center. Thus, only if the property field changes, such as by moving an atom having a non-zero property value, will the descriptors need to be recalculated. Additionally, a portion of the descriptors do relate to the underlying molecular structure, only these descriptors contain information from more than one reference point. In particular, a displacement is determined between a property field center and the centroid of a molecule. This descriptor contains information from two reference points. Furthermore, components of a property field are mapped onto a principal geometric frame, which essentially references the property field to the molecular shape.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventor: Benjamin D. Silverman
  • Patent number: 6518136
    Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kam Leung Lee, Ying Zhang, Maheswaran Surendra, Edmund M. Sikorski
  • Patent number: 6470361
    Abstract: A method and apparatus are provided for the efficient management of remembered sets in a generational garbage collection scheme. The present invention detects when an old object has a pointer to a young object, and needs to be added to the remembered set. A write buffer and a temporary buffer are used to create and maintain the remembered set. Entries in the write and temporary buffers are used as part of the root set for creating the remembered set for the next garbage collection. A barrier bit associated with each object differentiates generations in the generational garbage collection scheme and is used to determine whether to make an entry into a write buffer when a reference to another object is stored into an object. Objects that have survived one or more collections, but not the minimum number, N, of collections to be considered an old object are referred to as “middle-aged” objects. During a minor garbage collection, the write buffer is scanned.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: October 22, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bowen Alpern, Clement Richard Attanasio, Stephen Edwin Smith
  • Patent number: 6333247
    Abstract: A method of manufacturing a metal-oxide-semiconductor field effect transistor MOSFET device gate includes patterning and etching the mesa of a gate material. A dielectric layer is formed on the mesa and is planarized using chemical mechanical polishing (CMP). The active gate dimension is patterned and etched to form source and drain wells that extend down to an active area on either side of the MOSFET gate. In one further embodiment, the wells are filled with metal and the metal is planarized. The MOSFET device, in one embodiment, includes source and drain wells equally spaced from the active gate.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Erin C. Jones, Paul M. Solomon
  • Patent number: 6314193
    Abstract: A method and a device for the identification of plastic strips and/or window areas on mail is presented. The problem of dust build-up on the arrangement, causing it to fail, is avoided because the components can be arranged at a sufficient distance from the surface of the mail.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corporation
    Inventor: Manfred Vodegel
  • Patent number: 6288722
    Abstract: The present invention allows the frame buffer to be dynamically reconfigurable during the processing of graphics data. Lower resolution double buffer mode is used when objects are moving, and higher resolution single buffer mode is used when objects are stationary. The user gets the benefits of double buffering while objects are in motion, and the benefit of a higher quality image when objects are stationary. No image tears appear in this case because the graphics processing system redraws the exact same image when motion ceases, however the image has more bits per pixel. The visual effect is that the picture becomes clearer when motion ceases. The graphics processor quickly switches frame buffer modes during execution, and is not constrained to specifying one mode at the start of processing.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: September 11, 2001
    Assignee: International Business Machines Corporation
    Inventor: Chandrasekhar Narayanaswami
  • Patent number: 6274916
    Abstract: A method and structure for a field effect transistor (FET) includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate region, and a gate oxide region separating the gate region from other regions of the FET. The channel region is a Mott insulator. The gate oxide region is thicker than the channel region, and the gate oxide region includes a higher dielectric permittivity than the Mott insulator material.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: August 14, 2001
    Assignee: International Business Machines Corporation
    Inventors: Wilm E. Donath, Dennis M. Newns, Pratap C. Pattnaik
  • Patent number: 6255671
    Abstract: A structure includes a metal nitride film of the form MN, where M is selected from the group consisting of Ga, In, AlGa, AlIn, and AlGaIn. The structure has at least one electrically conductive metal region that is formed within and from the metal nitride film by a thermal process driven by absorption of light having a predetermined wavelength. Single films comprised of AlN are also within the scope of this invention, wherein an Al trace or interconnect is formed by laser radiation of wavelength 248 nm so as to contact circuitry that exists under the film. Multilayered stacks of films are also within the scope of the teachings of this invention.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: July 3, 2001
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Supratik Guha, Arunava Gupta, Sampath Purushothaman
  • Patent number: 6245005
    Abstract: The invention allows more accurate localization of radiation volumes during radiation treatment of tumors. The equipment includes radiation detector elements placed behind the patient during radiation, for treatment of a tumor condition. Such a detector may be constructed of semiconductor or a scintillating material. The radiation treatment plan for the patient includes an additional calculation of the treatment beam energy required for to enable the treatment beam to transit the patient. The energy required for patient transit is then measured, using a treatment beam with a beam current below that which will induce significant tissue damage. The experimental transit flux is then compared to the calculated transit flux, and the difference is used to correct the beam transport parameters in the original radiation treatment plan. Hence lower radiation doses and smaller radiation volumes can be achieved, reducing deleterious radiation side effects.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: June 12, 2001
    Assignee: International Business Machines Corporation
    Inventors: Robert Jacob von Gutfeld, James Francis Ziegler
  • Patent number: 6224690
    Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: May 1, 2001
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Madhav Datta, Hariklia Deligianni, Wilma Jean Horkans, Sung Kwon Kang, Keith Thomas Kwietniak, Gangadhara Swami Mathad, Sampath Purushothaman, Leathen Shi, Ho-Ming Tong