Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a plurality of dynamic logic circuits each performing a Boolean function on a plurality of inputs and generating an output on a dynamic node. The corresponding plurality of dynamic outputs are coupled to a static logic circuit which performs an additional Boolean function of the plurality of dynamic outputs. The static logic circuit operates to generate an output logic state that is maintained so long as the value of the Boolean operations being performed by the logic device do not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element.