Abstract: The present invention includes a novel audio recognition peripheral system and method. The audio recognition peripheral system comprises an audio recognition peripheral a programmable processor such as a microprocessor or microcontroller. In one embodiment, the audio recognition peripheral includes a feature extractor and vector processor. The feature extractor receives an audio signal and extracts recognition features. The extracted audio recognition features are transmitted to the programmable processor and processed in accordance with an audio recognition algorithm. During execution of the audio recognition algorithm, the programmable processor signals the audio recognition peripheral to perform vector operations. Thus, computationally intensive recognition operations are advantageously offloaded to the peripheral.

Abstract: The present invention provides a system and method for communicating data between network subsystems over optical fibers using a backchannel probe signal. In one embodiment, the present invention includes an optical network having an optical fiber coupled between first and second optical couplers residing in two different subsystems. A first processing unit is coupled to a first tap of the first optical coupler for providing an optical payload signal, and a second processing unit is coupled to a first tap of the second optical coupler for receiving the optical payload signal. A probe signal transmitter is coupled to a second tap of the second optical coupler for providing a probe signal, and a probe signal receiver coupled to a second tap of the first optical coupler for receiving the probe signal. The probe signal may be used to detect erroneous fiber connections or lossy inter-subsystem fibers.

Abstract: In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

Abstract: A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.

Abstract: A voltage controlled current source circuit of the present invention includes first reference current coupled to a voltage control node. A current input of a voltage controlled impedance is reproduced at the voltage control node through a current mirror as a second reference current. The voltage resulting from the action of the first and second reference currents is coupled to a voltage control input of the voltage controlled impedance. In one embodiment, a control voltage is provided to the gate of a transistor. The source of the transistor is coupled to the current input of a second voltage controlled impedance circuit to produce an output current at the drain of the transistor. The second voltage controlled impedance circuit has a voltage control input coupled to the voltage control input of the first voltage controlled impedance and to the voltage control node.