Patents Represented by Attorney Charles A. Burrell
  • Patent number: 7112285
    Abstract: Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventor: Kishore K. Chakravorty