Abstract: A method and apparatus for selectively providing hierarchy to a circuit design. The present invention contemplates providing a number of hierarchical statements in a description of a circuit design, wherein the syntax of the hierarchical statements allows the hierarchical statements to be visible when providing a first representation of the circuit design and effectively invisible when providing a second representation of the circuit design.

Abstract: A system and method which allows the interchange of Cookie information and standard Common Gateway Interface (CGI) variables between a user system and an On-Line Transaction Processing (OLTP) enterprise server. The present invention also discloses a specialized form of a transaction gateway, known as a security gateway, which runs on a Windows NT or UnixWare Web Server machine, and is built as a client application to interoperate with an enterprise-based OLTP security service. Finally, the present invention discloses an enterprise-based OLTP security service, which is used in conjunction with the security gateway described above, which processes user generated authentication requests, and if successful, calls an end service requested by a user.

Abstract: An apparatus for and method of utilizing an Internet terminal coupled to the world wide web to create multiple applications for accessing an existing proprietary data base management system. A dynamic tracing facility permits the developer to debug the applications using a common trace capability which processes and stores information from the trace of the applications within a common storage facility. The trace process is divided into two major components. A generic trace formatting module processes all trace results from various applications into a standardized format for storage and subsequent use. The second component is a generic policy in which the developer can present the trace parameters of a particular unique application in a standardized form. To store trace information from a plurality of applications into a common storage area, each of the applications is provided with a common identifier within the trace parameters.

Abstract: The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.

Abstract: An apparatus for and method of utilizing an internet terminal coupled to the world wide web to access an existing proprietary data base management system having a dialog-based request format. The user transmits a URL which is utilized to address one of a number of administrative objects. The addressed administrative object corresponds to one of a number of connection pools. The data base access is made from the connection pool. One of a number of runtime objects also corresponds directly to the one connection pool. Thus, the access attributes of the internet terminal may be modified during a single session.

Abstract: A placement tool that may import and export cell substitution and/or cell selection lists. The cell substitution and/or cell selection lists may be used by the placement tool to substitute and/or modify the placement design database, rather than the original schematic or behavioral database. This may eliminate the need to re-synthesize the circuit design during each design iteration. The present invention further contemplates providing a reset feature which may reset the circuit design database to a previous state, if desired.

Abstract: Method and apparatus for tracking messages and transactions communicated between a number of users and a number of hosts, where the hosts are executing concurrent applications. During a first user session, a first user communicates with a first host. A counter associated with the first user session is incremented when the application creates an output message. The counter is decremented when the output message is released to the first user. A flag associated with the first user session is set and the counter is incremented once the flag is set, if an input message or committing transaction is received from the first user. The flag is cleared and the counter is decremented when the input message or committing transaction is processed by the concurrent application. The counter being decremented indicates there are no dependencies during the first user session with regard to the output message, input message, or committing transaction.

Abstract: A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system.

Abstract: A system and method for managing a pool of threads for executing thread operations. A thread pool is instantiated which includes a plurality of threads, and a work queue having program controllable states is instantiated. Thread operations are queued to the work queue when the work queue is in a running or suspended state, and when the work queue is in a stopped state requests to queue thread operations are denied. The work queue supports controlled allocation of thread resources to a variety of thread operations.

Abstract: Methods for calculating mass storage requirements for a relational database table including both data pages and index pages. The methods allow direct calculation of the data storage and index storage requirements for a data base table, the methods based in part on the page size, the record length, and the number of records. The database requirement can be increased by partial unavailability of pages and rows. The methods include methods for calculating the number of B-tree levels in the index or indexes. The methods avoid the need for interactive calculations of the required size for a database table starting from the number of records, record size, and page size.

Abstract: A method and apparatus is disclosed for initiating execution of selected application processors in a clustered multiprocessor system without disrupting the addressing mode of the processors. In one embodiment, this is accomplished by initializing the processors in a conventional way, setting the addressing mode, and then leaving each of the processors in an active mode spinning on a designated Startup Address Location. To start an application processor, the OS simply write a target processor ID and a desired start-up address into the Startup Address Location. The application processor with the matching processor ID reads the Startup Address Location, jumps to the address specified in the Start-Up Address code section, and begins execution at that location. In another embodiment, a processor is provided that does not switch addressing modes when switched from a halt state.

Abstract: A method and apparatus for efficiently selecting cells within a circuit design database. The invention includes four primary features for selecting cells including (1) selecting only those cells that are in a pre-identified region and within a pre-identified selection area; (2) maneuvering through the circuit design hierarchy and selecting cells or regions at selected levels of hierarchy by using predetermined up and down hot-keys; (3) sorting selected cells by instance name, and manually selecting a desired cell or region from the resulting sorted list; and (4) sorting selected cells by a corresponding net name, and manually selecting a desired cell or region from the resulting sorted list.

Abstract: A system and methodology for implementing user assistance functions concerning interoperability of diverse applications, whether hosted on the same computer platform or hosted on different, and possibly heterogeneous computer platforms. The user is assisted by being offered information, tools and/or automation as appropriate to the problem presented. As appropriate, graphics or animation is utilized to permit complete and full understanding by the user of the assistance being provided.

Abstract: Method and apparatus for providing a hyperlink within a computer program that access information outside of the computer program. In a preferred embodiment, the hyperlink is provided in a first help file within a first autonomous computer program, wherein the hyperlink references information in a second help file. The activation of the hyperlink causing a second autonomous computer program to access and display the second help file to the user.

Abstract: A method and apparatus for increasing the routing bandwidth of interrupts between cluster manager devices in a clustered multiprocessor system is disclosed. This is accomplished by providing special cluster manager devices that can convert “N” serial messages received from a local APIC to “M” parallel messages, wherein M is less than N. The special cluster manager device then transfers the “M” parallel messages to a receiving cluster manager device. The receiving cluster manager device converts the “M” parallel messages into the original “N” serial messages, and sends the “N” serial messages to the appropriate local APIC within the receiving cluster.

Abstract: An apparatus for and method of utilizing an internet terminal coupled to the world wide web to access an existing proprietary data base management system having a dialog-based request format. The user request is received by a web server from the world wide web and converted into one or more sequenced data base management commands. These data base management commands are sequentially presented to the data base management system and the intermediate products stored. After all of the sequenced data base management commands have been executed, the web server combines the intermediate products to form a complete response to the initial user request. The response is transferred to the user over the world wide web as an HTML display page. The server automatically adds a footer text to the response if enabled by the system settings. The footer text may be created and modified from the internet terminal.

Abstract: An apparatus and method of efficiently recovering from physical disk drive (or logical file) failures in transaction based digital data processing systems. As transactions are sequentially processed, compacted audit trail records are prepared to indicate modifications resulting from each transaction. The audit trail records are stored in storage areas on a disk drive in accordance with the physical data base disk drive(s) or logical file(s) to which the corresponding transaction refers. A physical disk drive or logical file is dumped to magnetic tape whenever the associated audit trail storage area is full, thus clearing the audit trail storage area for further use. When a physical disk drive or logical file fails, the most recent dump is read. Modifications to each file of the dump are made as compacted audit trail data is processed. The modified files are destaged to a spare disk drive.

Abstract: Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.

Abstract: An improved rework method and rework wiring structure for repairing and reworking multilayer printed circuit boards utilizing ball grid array (BGA) solder pads are described. The repair method includes the steps of locating a solder pad to be rewired, removing the identified pad, installing a repair wire through a via hole in a multilayer printed circuit board, and forming a replacement solder pad on the end of the repair wire and positioning it in place of the removed pad. Once thus installed, the method includes the step of connecting the other end of the repair wire to a corrected circuit interconnection point.

Abstract: A computerized method enabling a user to specify and select a server for a database management system. The computerized method can include software modules for specifying the hardware required to handle the database and the transaction processing. The hardware required to handle the database such as the mass storage and memory can be estimated using either estimated or detailed inputs. When using the detailed inputs, the database composition of each table can be described in great detail, including details about the columns and rows. The hardware required to handle the transaction processing such as the number of processors and the LAN speed can be estimated using either the required transactions per second or the detailed SQL composition for each transaction. A comparator function can allow comparison between two systems in terms of performance ratios and price to performance ratios.