Abstract: A test driver for use in validating an electronic circuit design is disclosed. The test driver not only provides stimulus and verifies the response of a circuit design, but also responds appropriately to requests provided by the circuit design. The test driver may also modify a selected portion of a data element before returning the data element to the circuit design. Under some test conditions, this helps verify that the test driver did in fact gain access to a data element during a particular test case.

Abstract: Method and apparatus for a new interface architecture which reduces the number of software components required to interface a variety of requester types coupled to a server with a variety of communications programs coupled to an on-line transaction processing system. The new interface architecture isolate attributes of the requesters and the communication programs into individual software components so that all software code associated with each requester type is included within a corresponding requester software module, and all software code associated with each communications program is included within a corresponding communications software module. Each new requester type added requires the addition of only one requester software module, and each new communications program added requires the addition of only one communications software module, thus reducing the overall number of software modules required to interface the variety of requester types to the variety of communications programs.

Abstract: Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases the transfer rate of the interface by multiplexing two data groups on the same interface. These data groups are transmitted from a source phase latch at approximately the same time as two strobe signals which have low skew with respect to the data. The master and slave strobe signals are logically combined to create an even latch enable signal and an odd latch enable signal that are used to latch and de-multiplex the multiplexed data groups at a receiving end of a pair of flow-though source synchronous latches.

Abstract: A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device.

Abstract: A merge join process combines rows from an inner and an outer table when the inner table is indexed on a data column that is common to both tables. The merge join process creates a set of rows from the outer table that satisfy a selection criteria and sorts the rows in the set on the common data column if necessary. The merge join process searches for a matching inner row for each outer row in sequence using the inner table indices until it finds a matching inner row on a data page. The data page is then repeatedly searched for matches on the successive outer rows in the set until the end of the data page is reached. The end of the data page is reached when the value of the common data column in an outer row is greater than a last key that represents the highest value of the common data column in a inner row stored on the data page.

Abstract: A new distributed control mechanism for managing bi-directional interfaces of symmetrical multiprocessor systems in such a manner as to minimize the latency to storage, yet fairly distribute the use of the interfaces amongst the various components. This bi-directional interface can be designed to perform with differing characteristics depending upon the direction of information flow. These characteristics are implemented into the control logic of the source and destination components interconnected by the bi-directional interface, thus yielding two interface behaviors using only one interface. Each component is able to track the state of the interface by using only its own request state in conjunction with the detected request state of the opposing component, when both units are operating under the joint control algorithm present in the control logic of the source and destination component.

Abstract: A control system and interface is provided for controlling the transmission of address and data signals via independently operative bi-directional address and data interfaces, respectively, within a data processing system. The system allows address signals to be transferred via the address interface either before, or after, associated data signals are transferred. The address interface operates at a rate which is independent of the rate achieved on the data interface. Address signals transferred on the address interface are stored in one of a plurality of address storage devices depending on request type. A routing circuit associates later-provided data signals with the address storage device storing the associated address signals, and a correlation circuit allows the address storage device to record the data transfer with the associated address signals. According to one embodiment, the correlation is performed using a pointer indicative of a storage location temporarily storing the data signals.

Abstract: A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first device to a second local memory in a second device in a transaction processing system that includes a main memory to provide supervisory storage capability for the transaction processing system, and a directory storage for maintaining ownership status of each data segment of the main memory. A data transfer of a requested data segment is requested by the second device to obtain the requested data segment stored in the first local memory of the first device. The requested data segment is removed from the first local memory in response to the data transfer request, and is directly transferred to the second local memory of the second device.

Abstract: A system and method is provided for selectively injecting interrupts within the instruction stream of a data processing system. The system includes a programmable storage device for storing interrupt injection signals, each of which is associated with a respective machine instruction. When execution of the associated machine instruction is initiated, the stored signal is read from the storage device and is made available to the interrupt logic within the instruction processor. If set to a predetermined logic level, the signal causes an interrupt to be injected within the instruction processor. The system provides the capability to simultaneously inject different types of interrupts, including fault and non-fault interrupts, during the execution of any instruction. The invention further provides a programmable means for injecting errors at predetermined intervals in the instruction stream.

Abstract: A system and method for providing transaction indivisibility in a transaction processing system through the use of commonly-accessible modules for monitoring and maintaining proper source message sequencing is provided. A source message is transmitted from the host processing unit upon recovery of a failure of the host processing unit, where the source message includes information destined for the database, and an identifying sequence number. The identifying sequence number is compared to a stored sequence number, where the stored sequence number is associated with an immediately preceding source message received prior to the failure of the host processing unit. A source message indivisibility failure is indicated where the identifying sequence number is not consecutive with respect to the stored sequence number, while the source message is added to a message execution queue if the identifying sequence number is consecutive with respect to the stored sequence number.

Abstract: Method and apparatus for providing a timely, automated re-assignment of resources, such as peripheral devices, memory, and/or processing capacity, among a number of host data processing systems. In a preferred embodiment, the present invention allows peripheral devices, such as tape drives, to be configured as shareable units, and accessed by any participating host data processing system as the need arises. The invention preferably includes a central coordinating facility, which evaluates the device status information gathered, from each participating host data processing system. The device status information is used to determine which host data processing systems have free devices available for use. Within these constraints, the invention automatically orchestrates the re-assignment of selected peripheral devices from where they are not currently needed to where they are needed, with little or no operator interaction.

Abstract: A method for detecting the most likely source of an error in a document image processing system which processes sets of related documents. A set of characteristics is selected as being indicative that the document image, or item, is the source of the error. Each of the characteristics is assigned a weight, wherein the weight is in proportion to the likelihood that an item exhibiting the characteristic is the source of error. The items are ranked according to the characteristics exhibited by each item.

Abstract: A method and apparatus for efficiently debugging and/or testing a rules based expert system. To provide guidance when updating a test sequence, the present invention contemplates identifying which rule sets and/or rules were exercised by the test sequence, and which were not exercised. The present invention also contemplates identifying the rule sets and/or rules that were exercised, and the percent of the rule sets/rules that were exercised. This and other information may be useful in identifying appropriate changes for the test sequence so that those rule sets and/or rules that were not exercised during the previous iteration are exercised in a subsequent iteration.

Abstract: Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory.

Abstract: A method and apparatus for reducing processor response time to selected transfer instructions in an multi-instruction processor. The response time is shortened by using a fast path to generate addresses for selected transfer instructions. In this fast path a base address, retained in a register from a previous instruction, is summed with an offset from the current instruction to obtain an absolute address for memory accessing. Before the fast path is entered determinations are made whether the instruction is a particular transfer instruction of a particular class and subclass, and whether the base address is different than the base address for the previous instruction. Even through the fast path is entered the usual absolute address generator path is also entered where the instruction is subjected to both high and low limit tests.

Abstract: A system and method for assembling database restoration data according to transaction in a transaction processing system. Database restoration data is collated by chronologically storing updated database records in distinct storage banks partitioned according to its corresponding transaction. Resulting database record blocks from storage banks associated with completed database transactions are queued in the order that their corresponding transactions were completed. The queued database record blocks are transferred to storage media, whereby the queued database record blocks are arranged on the storage media according to transaction, and in the order that the active transactions were completed.

Abstract: A method and apparatus for reducing processor response time to selected transfer instructions in an instruction processor using a plurality of memory banks including four banks in a basic mode and one memory bank in an extended mode. This invention provides fast transfer hardware to improve the response time by a speed up transfer for normal extended mode transfer instructions only. The bank descriptor of the instruction is used to determine appropriate transfer instructions which are then tested for characteristics indicating whether a fast transfer is possible. The fast transfer process requires fewer checks than the previous apparatus which accelerates the response to selected transfer instructions by one cycle.

Abstract: Method and apparatus for providing backup memory storage for audit trail data within a computer system having a main memory storage, a non-volatile memory storage, and backup memory storage. The computer system executes a number of transaction programs which generate audit trail entries. As the audit trail entries are generated, a portion of the audit trail entries are stored in a portion of the main memory storage to create an audit trail. The audit trail entries are accumulated in the portion of the main memory storage until a request is received to write the portion of the main memory storage to a corresponding portion of the non-volatile memory. Subsequent portions of the audit trail entries are accumulated in subsequent portions of the main memory storage.

Abstract: An improved tilt-bed trailer constructed of light weight and durable materials is disclosed. A trailer frame with an associated rotatably interconnected tongue is affixed with a tongue release and retention mechanism that slidably engages a portion of the tongue and a portion of the frame to hold them in a fixed position when engaged and to allow the frame to pivot with respect to the tongue when disengaged. The mechanism utilizes gripping members to cooperate with ridges on the tongue.